diff options
| -rw-r--r-- | zjit/src/disasm.rs | 31 | ||||
| -rw-r--r-- | zjit/src/lib.rs | 9 |
2 files changed, 12 insertions, 28 deletions
diff --git a/zjit/src/disasm.rs b/zjit/src/disasm.rs index f18fad1ae0..d8e0dc690c 100644 --- a/zjit/src/disasm.rs +++ b/zjit/src/disasm.rs @@ -1,25 +1,19 @@ +use std::fmt::Write; + #[cfg(feature = "disasm")] -pub fn disasm_addr_range(cb: &CodeBlock, start_addr: usize, end_addr: usize) -> String { +pub fn disasm_addr_range(start_addr: usize, end_addr: usize) -> String { let mut out = String::from(""); // Initialize capstone use capstone::prelude::*; - #[cfg(target_arch = "x86_64")] + // TODO: switch the architecture once we support Arm let mut cs = Capstone::new() .x86() .mode(arch::x86::ArchMode::Mode64) .syntax(arch::x86::ArchSyntax::Intel) .build() .unwrap(); - - #[cfg(target_arch = "aarch64")] - let mut cs = Capstone::new() - .arm64() - .mode(arch::arm64::ArchMode::Arm) - .detail(true) - .build() - .unwrap(); cs.set_skipdata(true).unwrap(); // Disassemble the instructions @@ -29,26 +23,11 @@ pub fn disasm_addr_range(cb: &CodeBlock, start_addr: usize, end_addr: usize) -> #[cfg(test)] let start_addr = 0; let insns = cs.disasm_all(code_slice, start_addr as u64).unwrap(); - let colors = get_colors(); // For each instruction in this block for insn in insns.as_ref() { - // Comments for this block - if let Some(comment_list) = cb.comments_at(insn.address() as usize) { - for comment in comment_list { - if cb.outlined { - write!(&mut out, "{}", colors.blue_begin).unwrap(); // Make outlined code blue - } - writeln!(&mut out, " {}# {comment}{}", colors.bold_begin, colors.bold_end).unwrap(); // Make comments bold - } - } - if cb.outlined { - write!(&mut out, "{}", colors.blue_begin).unwrap(); // Make outlined code blue - } + // TODO: support comments writeln!(&mut out, " {insn}").unwrap(); - if cb.outlined { - write!(&mut out, "{}", colors.blue_end).unwrap(); // Disable blue - } } return out; diff --git a/zjit/src/lib.rs b/zjit/src/lib.rs index 511999f9b7..db3dd11b87 100644 --- a/zjit/src/lib.rs +++ b/zjit/src/lib.rs @@ -84,11 +84,16 @@ pub extern "C" fn rb_zjit_iseq_gen_entry_point(iseq: IseqPtr, _ec: EcPtr) -> *co let cb = ZJITState::get_code_block(); let start_ptr = cb.get_write_ptr(); x86_emit(cb); - let _end_ptr = cb.get_write_ptr(); #[cfg(feature = "disasm")] { - let _disasm = disasm_addr_range(); + let end_ptr = cb.get_write_ptr(); + + use disasm::disasm_addr_range; + let disasm = disasm_addr_range(start_ptr.raw_ptr(cb) as usize, end_ptr.raw_ptr(cb) as usize); + if false { // TODO: implement the option + println!("{}", disasm); + } } if cfg!(target_arch = "x86_64") { |