diff options
| -rw-r--r-- | .cirrus.yml | 11 | ||||
| -rw-r--r-- | yjit/src/backend/arm64/mod.rs | 2 |
2 files changed, 12 insertions, 1 deletions
diff --git a/.cirrus.yml b/.cirrus.yml index ef91abd3b2..839b4a6c17 100644 --- a/.cirrus.yml +++ b/.cirrus.yml @@ -153,4 +153,15 @@ yjit_task: bootstraptest/test_struct.rb \ bootstraptest/test_yjit_new_backend.rb \ bootstraptest/test_yjit_rust_port.rb + + # These are the btests we can't run yet on arm: + #bootstraptest/test_block.rb (missing opt_send) + #bootstraptest/test_insns.rb (missing opt_send) + #bootstraptest/test_literal.rb (displacement bug) + #bootstraptest/test_syntax.rb (missing opt_send) + #bootstraptest/test_thread.rb (deadlock) + #bootstraptest/test_yjit.rb (multiple bugs) + #bootstraptest/test_yjit_30k_ifelse.rb (missing opt_send) + #bootstraptest/test_yjit_30k_methods.rb (missing opt_send) + # full_build_script: make -j diff --git a/yjit/src/backend/arm64/mod.rs b/yjit/src/backend/arm64/mod.rs index 99cf08c09c..e0e889c16c 100644 --- a/yjit/src/backend/arm64/mod.rs +++ b/yjit/src/backend/arm64/mod.rs @@ -66,7 +66,7 @@ impl Assembler /// Note: we intentionally exclude C_RET_REG (X0) from this list /// because of the way it's used in gen_leave() and gen_leave_exit() pub fn get_alloc_regs() -> Vec<Reg> { - vec![X11_REG, X12_REG] + vec![X11_REG, X12_REG, X13_REG] } /// Get a list of all of the caller-saved registers |