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authorAiden Fox Ivey <aiden.foxivey@shopify.com>2025-09-02 17:27:31 -0400
committerTakashi Kokubun <takashikkbn@gmail.com>2025-09-02 15:57:14 -0700
commitefd2746b3f0b54aac77c568e4d09ed4d1b947c0b (patch)
treee89ba9a2e39ec3c4cc7928b6b8b6c6f88a2cb26f
parent8e8f2ba2b46a3b95c90f2b6b60480b3c5cd7c23e (diff)
ZJIT: Remove unnecessary .into calls
-rw-r--r--zjit/src/asm/mod.rs4
-rw-r--r--zjit/src/backend/arm64/mod.rs4
-rw-r--r--zjit/src/backend/lir.rs2
-rw-r--r--zjit/src/codegen.rs4
4 files changed, 7 insertions, 7 deletions
diff --git a/zjit/src/asm/mod.rs b/zjit/src/asm/mod.rs
index 5e582ce282..08d3571c2d 100644
--- a/zjit/src/asm/mod.rs
+++ b/zjit/src/asm/mod.rs
@@ -330,7 +330,7 @@ pub fn imm_num_bits(imm: i64) -> u8
return 32;
}
- return 64;
+ 64
}
/// Compute the number of bits needed to encode an unsigned value
@@ -347,7 +347,7 @@ pub fn uimm_num_bits(uimm: u64) -> u8
return 32;
}
- return 64;
+ 64
}
#[cfg(test)]
diff --git a/zjit/src/backend/arm64/mod.rs b/zjit/src/backend/arm64/mod.rs
index 584914c833..664e65f7aa 100644
--- a/zjit/src/backend/arm64/mod.rs
+++ b/zjit/src/backend/arm64/mod.rs
@@ -1107,8 +1107,8 @@ impl Assembler
// be stored is first and the address is second. However in
// our IR we have the address first and the register second.
match dest_num_bits {
- 64 | 32 => stur(cb, src.into(), dest.into()),
- 16 => sturh(cb, src.into(), dest.into()),
+ 64 | 32 => stur(cb, src, dest),
+ 16 => sturh(cb, src, dest),
num_bits => panic!("unexpected dest num_bits: {} (src: {:#?}, dest: {:#?})", num_bits, src, dest),
}
},
diff --git a/zjit/src/backend/lir.rs b/zjit/src/backend/lir.rs
index 068e3f69dc..03cd5253bc 100644
--- a/zjit/src/backend/lir.rs
+++ b/zjit/src/backend/lir.rs
@@ -1568,7 +1568,7 @@ impl Assembler
let side_exit_label = if let Some(label) = label {
Target::Label(label)
} else {
- self.new_label("side_exit".into())
+ self.new_label("side_exit")
};
self.write_label(side_exit_label.clone());
diff --git a/zjit/src/codegen.rs b/zjit/src/codegen.rs
index 270de31630..4494b23824 100644
--- a/zjit/src/codegen.rs
+++ b/zjit/src/codegen.rs
@@ -485,7 +485,7 @@ fn gen_defined(jit: &JITState, asm: &mut Assembler, op_type: usize, obj: VALUE,
let block_handler = asm.load(Opnd::mem(64, lep, SIZEOF_VALUE_I32 * VM_ENV_DATA_INDEX_SPECVAL));
let pushval = asm.load(pushval.into());
asm.cmp(block_handler, VM_BLOCK_HANDLER_NONE.into());
- asm.csel_e(Qnil.into(), pushval.into())
+ asm.csel_e(Qnil.into(), pushval)
} else {
Qnil.into()
}
@@ -1662,7 +1662,7 @@ fn gen_function_stub(cb: &mut CodeBlock, iseq_call: Rc<RefCell<IseqCall>>) -> Re
// Call function_stub_hit using the shared trampoline. See `gen_function_stub_hit_trampoline`.
// Use load_into instead of mov, which is split on arm64, to avoid clobbering ALLOC_REGS.
- asm.load_into(SCRATCH_OPND, Opnd::const_ptr(Rc::into_raw(iseq_call).into()));
+ asm.load_into(SCRATCH_OPND, Opnd::const_ptr(Rc::into_raw(iseq_call)));
asm.jmp(ZJITState::get_function_stub_hit_trampoline().into());
asm.compile(cb).map(|(code_ptr, gc_offsets)| {