Update disassembly snapshots for capstone 0.14.0

Capstone 0.14.0 uses canonical ARM64 aliases in its disassembly output:
- `orr x, xzr, #imm` is now shown as `mov x, #imm`
- `.byte` sequences matching `udf` are now decoded as `udf #imm`

These are cosmetic changes to the disassembly text only; the underlying
machine code (verified by hex snapshots) is unchanged.

Also update the root Cargo.lock which was missed by Dependabot.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

4 files changed, 21 insertions, 16 deletions

diff --git a/Cargo.lock b/Cargo.lock
index 9a4b2ebbba..c5c9ee9324 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -4,22 +4,21 @@ version = 3
 
 [[package]]
 name = "capstone"
-version = "0.13.0"
+version = "0.14.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "015ef5d5ca1743e3f94af9509ba6bd2886523cfee46e48d15c2ef5216fd4ac9a"
+checksum = "f442ae0f2f3f1b923334b4a5386c95c69c1cfa072bafa23d6fae6d9682eb1dd4"
 dependencies = [
  "capstone-sys",
- "libc",
+ "static_assertions",
 ]
 
 [[package]]
 name = "capstone-sys"
-version = "0.17.0"
+version = "0.18.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2267cb8d16a1e4197863ec4284ffd1aec26fe7e57c58af46b02590a0235809a0"
+checksum = "a4e8087cab6731295f5a2a2bd82989ba4f41d3a428aab2e7c98d8f4db38aac05"
 dependencies = [
  "cc",
- "libc",
 ]
 
 [[package]]
@@ -103,6 +102,12 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "32fea41aca09ee824cc9724996433064c89f7777e60762749a4170a14abbfa21"
 
 [[package]]
+name = "static_assertions"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a2eb9349b6444b326872e140eb1cf5e7c522154d69e7a0ffb0fb81c06b37543f"
+
+[[package]]
 name = "windows-sys"
 version = "0.52.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
diff --git a/yjit/src/backend/arm64/mod.rs b/yjit/src/backend/arm64/mod.rs
index 0521e09d0b..1712ad0302 100644
--- a/yjit/src/backend/arm64/mod.rs
+++ b/yjit/src/backend/arm64/mod.rs
@@ -1777,7 +1777,7 @@ mod tests {
 
         assert_disasm!(cb, "e1ff9fd2e10370b2", {"
             0x0: mov x1, #0xffff
-            0x4: orr x1, xzr, #0x10000
+            0x4: mov x1, #0x10000
         "});
     }
 
diff --git a/zjit/src/asm/arm64/mod.rs b/zjit/src/asm/arm64/mod.rs
index c30520cd69..154e7ebd19 100644
--- a/zjit/src/asm/arm64/mod.rs
+++ b/zjit/src/asm/arm64/mod.rs
@@ -1666,7 +1666,7 @@ mod tests {
     #[test]
     fn test_mov_immediate() {
         let cb = compile(|cb| mov(cb, X10, A64Opnd::new_uimm(0x5555555555555555)));
-        assert_disasm_snapshot!(cb.disasm(), @"  0x0: orr x10, xzr, #0x5555555555555555");
+        assert_disasm_snapshot!(cb.disasm(), @"  0x0: mov x10, #0x5555555555555555");
         assert_snapshot!(cb.hexdump(), @"eaf300b2");
     }
 
diff --git a/zjit/src/backend/arm64/mod.rs b/zjit/src/backend/arm64/mod.rs
index a1836ea9df..20e80ebcd1 100644
--- a/zjit/src/backend/arm64/mod.rs
+++ b/zjit/src/backend/arm64/mod.rs
@@ -1902,7 +1902,7 @@ mod tests {
         0x0: ldnp d8, d25, [x10, #-0x140]
         0x4: .byte 0x6f, 0x2c, 0x20, 0x77
         0x8: .byte 0x6f, 0x72, 0x6c, 0x64
-        0xc: .byte 0x21, 0x00, 0x00, 0x00
+        0xc: udf #0x21
         ");
         assert_snapshot!(cb.hexdump(), @"48656c6c6f2c20776f726c6421000000");
     }
@@ -2053,7 +2053,7 @@ mod tests {
 
         asm.compile_with_num_regs(&mut cb, 0);
         assert_disasm_snapshot!(cb.disasm(), @r"
-            0x0: orr x0, xzr, #0x7fffffff
+            0x0: mov x0, #0x7fffffff
             0x4: add x0, sp, x0
             0x8: mov x0, #8
             0xc: movk x0, #1, lsl #16
@@ -2069,7 +2069,7 @@ mod tests {
             0x34: movk x0, #0xffff, lsl #32
             0x38: movk x0, #0xffff, lsl #48
             0x3c: add x0, sp, x0
-            0x40: orr x0, xzr, #0xffffffff80000000
+            0x40: mov x0, #-0x80000000
             0x44: add x0, sp, x0
         ");
         assert_snapshot!(cb.hexdump(), @"e07b40b2e063208b000180d22000a0f2e063208b000083d2e063208be0230891e02308d1e0ff8292e063208b00ff9fd2c0ffbff2e0ffdff2e0fffff2e063208be08361b2e063208b");
@@ -2137,8 +2137,8 @@ mod tests {
         assert_disasm_snapshot!(cb.disasm(), @"
             0x0: ldr x16, #8
             0x4: b #0x10
-            0x8: .byte 0x00, 0x10, 0x00, 0x00
-            0xc: .byte 0x00, 0x00, 0x00, 0x00
+            0x8: udf #0x1000
+            0xc: udf #0
             0x10: stur x16, [x21]
         ");
         assert_snapshot!(cb.hexdump(), @"50000058030000140010000000000000b00200f8");
@@ -2200,7 +2200,7 @@ mod tests {
         0x8: ldnp d8, d25, [x10, #-0x140]
         0xc: .byte 0x6f, 0x2c, 0x20, 0x77
         0x10: .byte 0x6f, 0x72, 0x6c, 0x64
-        0x14: .byte 0x21, 0x00, 0x00, 0x00
+        0x14: udf #0x21
         0x18: stur x0, [x21]
         ");
         assert_snapshot!(cb.hexdump(), @"50000010e00310aa48656c6c6f2c20776f726c6421000000a00200f8");
@@ -2304,7 +2304,7 @@ mod tests {
         asm.compile_with_num_regs(&mut cb, 1);
 
         assert_disasm_snapshot!(cb.disasm(), @r"
-        0x0: orr x0, xzr, #0xffffffff
+        0x0: mov x0, #0xffffffff
         0x4: tst w0, w0
         ");
         assert_snapshot!(cb.hexdump(), @"e07f40b21f00006a");
@@ -2566,7 +2566,7 @@ mod tests {
 
         assert_disasm_snapshot!(cb.disasm(), @"
             0x0: mov x1, #0xffff
-            0x4: orr x1, xzr, #0x10000
+            0x4: mov x1, #0x10000
         ");
         assert_snapshot!(cb.hexdump(), @"e1ff9fd2e10370b2");
     }