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authorMaxime Chevalier-Boisvert <maxime.chevalierboisvert@shopify.com>2022-06-15 16:17:15 -0400
committerTakashi Kokubun <takashikkbn@gmail.com>2022-08-29 08:46:56 -0700
commit40ac79ada89953f5ed9e36bdb5b3d0d3ae8d8f3e (patch)
tree97163a1eda2b9f47930878768b02c69fc6820bc4
parentabea8c8983aef411f7e6a2afbfbc25e31b2f5486 (diff)
Add bitwise and to x86 backend
-rw-r--r--yjit/src/backend/x86_64/mod.rs4
1 files changed, 4 insertions, 0 deletions
diff --git a/yjit/src/backend/x86_64/mod.rs b/yjit/src/backend/x86_64/mod.rs
index 7dcf41600d..e4f8745583 100644
--- a/yjit/src/backend/x86_64/mod.rs
+++ b/yjit/src/backend/x86_64/mod.rs
@@ -134,6 +134,10 @@ impl Assembler
add(cb, insn.opnds[0].into(), insn.opnds[1].into())
},
+ Op::And => {
+ and(cb, insn.opnds[0].into(), insn.opnds[1].into())
+ },
+
Op::Store => mov(cb, insn.opnds[0].into(), insn.opnds[1].into()),
// This assumes only load instructions can contain references to GC'd Value operands