diff options
| author | Maxime Chevalier-Boisvert <maxime.chevalierboisvert@shopify.com> | 2022-06-15 13:24:21 -0400 |
|---|---|---|
| committer | Takashi Kokubun <takashikkbn@gmail.com> | 2022-08-29 08:46:56 -0700 |
| commit | 401521ca14da1b740be9004cc4a344925dbf5fff (patch) | |
| tree | 808ec31d42972beb3f775f49d4af8b4f670bfa44 | |
| parent | ae9bcfec8c237266e324fc1ae6a7a28390045b7e (diff) | |
Rename transform_insns to forward_pass
| -rw-r--r-- | yjit/src/backend/ir.rs | 6 | ||||
| -rw-r--r-- | yjit/src/backend/x86_64/mod.rs | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/yjit/src/backend/ir.rs b/yjit/src/backend/ir.rs index 1fca3a5b87..d14e3485aa 100644 --- a/yjit/src/backend/ir.rs +++ b/yjit/src/backend/ir.rs @@ -328,7 +328,7 @@ impl Assembler } /// Transform input instructions, consumes the input assembler - pub(super) fn transform_insns<F>(mut self, mut map_insn: F) -> Assembler + pub(super) fn forward_pass<F>(mut self, mut map_insn: F) -> Assembler where F: FnMut(&mut Assembler, usize, Op, Vec<Opnd>, Option<Target>) { let mut asm = Assembler { @@ -400,7 +400,7 @@ impl Assembler opnds.into_iter().map(|opnd| map_opnd(opnd, asm)).collect() } - self.transform_insns(|asm, _, op, opnds, target| { + self.forward_pass(|asm, _, op, opnds, target| { // Load heap object operands into registers because most // instructions can't directly work with 64-bit constants let opnds = load_gc_opnds(op, opnds, asm); @@ -478,7 +478,7 @@ impl Assembler let live_ranges: Vec<usize> = std::mem::take(&mut self.live_ranges); - let asm = self.transform_insns(|asm, index, op, opnds, target| { + let asm = self.forward_pass(|asm, index, op, opnds, target| { // Check if this is the last instruction that uses an operand that // spans more than one instruction. In that case, return the // allocated register to the pool. diff --git a/yjit/src/backend/x86_64/mod.rs b/yjit/src/backend/x86_64/mod.rs index 8c34b55832..daa8005088 100644 --- a/yjit/src/backend/x86_64/mod.rs +++ b/yjit/src/backend/x86_64/mod.rs @@ -74,7 +74,7 @@ impl Assembler { let live_ranges: Vec<usize> = std::mem::take(&mut self.live_ranges); - self.transform_insns(|asm, index, op, opnds, target| { + self.forward_pass(|asm, index, op, opnds, target| { match op { Op::Add | Op::Sub | Op::And | Op::Not => { match opnds[0] { |