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| author | Takashi Kokubun <takashi.kokubun@shopify.com> | 2025-07-02 10:46:08 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-02 10:46:08 -0700 |
| commit | 1d31c98e04098d406ae97fd51698533ab4933a0b (patch) | |
| tree | 9f548d727ed694b603cf8f206f7d65d91bbb46a6 | |
| parent | 6e28574ed08b076783035dc67ed0067550ff6bbe (diff) | |
ZJIT: Avoid panicing with "Option::unwrap() on None" (#13762)
| -rw-r--r-- | zjit/src/backend/lir.rs | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/zjit/src/backend/lir.rs b/zjit/src/backend/lir.rs index c168170b2f..4cc093ed5e 100644 --- a/zjit/src/backend/lir.rs +++ b/zjit/src/backend/lir.rs @@ -1525,7 +1525,12 @@ impl Assembler // Convert live_ranges to live_regs: the number of live registers at each index let mut live_regs: Vec<usize> = vec![]; for insn_idx in 0..insns.len() { - let live_count = live_ranges.iter().filter(|range| range.start() <= insn_idx && insn_idx <= range.end()).count(); + let live_count = live_ranges.iter().filter(|range| + match (range.start, range.end) { + (Some(start), Some(end)) => start <= insn_idx && insn_idx <= end, + _ => false, + } + ).count(); live_regs.push(live_count); } @@ -1561,7 +1566,8 @@ impl Assembler // If C_RET_REG is in use, move it to another register. // This must happen before last-use registers are deallocated. if let Some(vreg_idx) = pool.vreg_for(&C_RET_REG) { - let new_reg = pool.alloc_reg(vreg_idx).unwrap(); // TODO: support spill + let new_reg = pool.alloc_reg(vreg_idx) + .expect("spilling VReg is not implemented yet, can't evacuate C_RET_REG on CCall"); // TODO: support spilling VReg asm.mov(Opnd::Reg(new_reg), C_RET_OPND); pool.dealloc_reg(&C_RET_REG); reg_mapping[vreg_idx] = Some(new_reg); |
