1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
|
use super::{family::Family, sf::Sf};
/// The operation being performed by this instruction.
enum Op {
Add = 0b0,
Sub = 0b1
}
// Whether or not to update the flags when this instruction is performed.
enum S {
LeaveFlags = 0b0,
UpdateFlags = 0b1
}
/// The type of shift to perform on the second operand register.
enum Shift {
LSL = 0b00, // logical shift left (unsigned)
LSR = 0b01, // logical shift right (unsigned)
ASR = 0b10 // arithmetic shift right (signed)
}
/// The struct that represents an A64 data processing -- register instruction
/// that can be encoded.
///
/// Add/subtract (shifted register)
/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
/// | 0 1 0 1 1 0 |
/// | sf op S shift rm.............. imm6............... rn.............. rd.............. |
/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
///
pub struct DataProcessingRegister {
/// The register number of the destination register.
rd: u8,
/// The register number of the first operand register.
rn: u8,
/// The amount to shift the second operand register by.
imm6: u8,
/// The register number of the second operand register.
rm: u8,
/// The type of shift to perform on the second operand register.
shift: Shift,
/// Whether or not to update the flags when this instruction is performed.
s: S,
/// The opcode for this instruction.
op: Op,
/// Whether or not this instruction is operating on 64-bit operands.
sf: Sf
}
impl DataProcessingRegister {
/// ADD (shifted register)
/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADD--shifted-register---Add--shifted-register--?lang=en
pub fn add(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
Self {
rd,
rn,
imm6: 0,
rm,
shift: Shift::LSL,
s: S::LeaveFlags,
op: Op::Add,
sf: num_bits.into()
}
}
/// ADDS (shifted register, set flags)
/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADDS--shifted-register---Add--shifted-register---setting-flags-?lang=en
pub fn adds(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
Self {
rd,
rn,
imm6: 0,
rm,
shift: Shift::LSL,
s: S::UpdateFlags,
op: Op::Add,
sf: num_bits.into()
}
}
/// SUB (shifted register)
/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUB--shifted-register---Subtract--shifted-register--?lang=en
pub fn sub(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
Self {
rd,
rn,
imm6: 0,
rm,
shift: Shift::LSL,
s: S::LeaveFlags,
op: Op::Sub,
sf: num_bits.into()
}
}
/// SUBS (shifted register, set flags)
/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUBS--shifted-register---Subtract--shifted-register---setting-flags-?lang=en
pub fn subs(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
Self {
rd,
rn,
imm6: 0,
rm,
shift: Shift::LSL,
s: S::UpdateFlags,
op: Op::Sub,
sf: num_bits.into()
}
}
}
impl From<DataProcessingRegister> for u32 {
/// Convert an instruction into a 32-bit value.
fn from(inst: DataProcessingRegister) -> Self {
let imm6 = (inst.imm6 as u32) & ((1 << 6) - 1);
0
| ((inst.sf as u32) << 31)
| ((inst.op as u32) << 30)
| ((inst.s as u32) << 29)
| ((Family::DataProcessingRegister as u32) << 25)
| (1 << 24)
| ((inst.shift as u32) << 22)
| ((inst.rm as u32) << 16)
| (imm6 << 10)
| ((inst.rn as u32) << 5)
| inst.rd as u32
}
}
impl From<DataProcessingRegister> for [u8; 4] {
/// Convert an instruction into a 4 byte array.
fn from(inst: DataProcessingRegister) -> [u8; 4] {
let result: u32 = inst.into();
result.to_le_bytes()
}
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_add() {
let inst = DataProcessingRegister::add(0, 1, 2, 64);
let result: u32 = inst.into();
assert_eq!(0x8b020020, result);
}
#[test]
fn test_adds() {
let inst = DataProcessingRegister::adds(0, 1, 2, 64);
let result: u32 = inst.into();
assert_eq!(0xab020020, result);
}
#[test]
fn test_sub() {
let inst = DataProcessingRegister::sub(0, 1, 2, 64);
let result: u32 = inst.into();
assert_eq!(0xcb020020, result);
}
#[test]
fn test_subs() {
let inst = DataProcessingRegister::subs(0, 1, 2, 64);
let result: u32 = inst.into();
assert_eq!(0xeb020020, result);
}
}
|
