38 files changed, 6015 insertions, 0 deletions

diff --git a/zjit/src/asm/arm64/README.md b/zjit/src/asm/arm64/README.md
new file mode 100644
index 0000000000..6adfad804d
--- /dev/null
+++ b/zjit/src/asm/arm64/README.md
@@ -0,0 +1,16 @@
+# Arm64
+
+This module is responsible for encoding ZJIT operands into an appropriate Arm64 encoding.
+
+## Architecture
+
+Every instruction in the Arm64 instruction set is 32 bits wide and is represented in little-endian order. Because they're all going to the same size, we represent each instruction by a struct that implements `From<T> for u32`, which contains the mechanism for encoding each instruction. The encoding for each instruction is shown in the documentation for the struct that ends up being created.
+
+In general each set of bytes inside of the struct has either a direct value (usually a `u8`/`u16`) or some kind of `enum` that can be converted directly into a `u32`. For more complicated pieces of encoding (e.g., bitmask immediates) a corresponding module under the `arg` namespace is available.
+
+## Helpful links
+
+* [Arm A64 Instruction Set Architecture](https://developer.arm.com/documentation/ddi0596/2021-12?lang=en) Official documentation
+* [armconverter.com](https://armconverter.com/) A website that encodes Arm assembly syntax
+* [hatstone](https://github.com/tenderlove/hatstone) A wrapper around the Capstone disassembler written in Ruby
+* [onlinedisassembler.com](https://onlinedisassembler.com/odaweb/) A web-based disassembler
diff --git a/zjit/src/asm/arm64/arg/bitmask_imm.rs b/zjit/src/asm/arm64/arg/bitmask_imm.rs
new file mode 100644
index 0000000000..70a439afd5
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/bitmask_imm.rs
@@ -0,0 +1,255 @@
+/// Immediates used by the logical immediate instructions are not actually the
+/// immediate value, but instead are encoded into a 13-bit wide mask of 3
+/// elements. This allows many more values to be represented than 13 bits would
+/// normally allow, at the expense of not being able to represent every possible
+/// value.
+///
+/// In order for a number to be encodeable in this form, the binary
+/// representation must consist of a single set of contiguous 1s. That pattern
+/// must then be replicatable across all of the bits either 1, 2, 4, 8, 16, or
+/// 32 times (rotated or not).
+///
+/// For example, 1 (0b1), 2 (0b10), 3 (0b11), and 4 (0b100) are all valid.
+/// However, 5 (0b101) is invalid, because it contains 2 sets of 1s and cannot
+/// be replicated across 64 bits.
+///
+/// Some more examples to illustrate the idea of replication:
+/// * 0x5555555555555555 is a valid value (0b0101...) because it consists of a
+///   single set of 1s which can be replicated across all of the bits 32 times.
+/// * 0xf0f0f0f0f0f0f0f0 is a valid value (0b1111000011110000...) because it
+///   consists of a single set of 1s which can be replicated across all of the
+///   bits 8 times (rotated by 4 bits).
+/// * 0x0ff00ff00ff00ff0 is a valid value (0000111111110000...) because it
+///   consists of a single set of 1s which can be replicated across all of the
+///   bits 4 times (rotated by 12 bits).
+///
+/// To encode the values, there are 3 elements:
+/// * n = 1 if the pattern is 64-bits wide, 0 otherwise
+/// * imms = the size of the pattern, a 0, and then one less than the number of
+///   sequential 1s
+/// * immr = the number of right rotations to apply to the pattern to get the
+///   target value
+///
+pub struct BitmaskImmediate {
+    n: u8,
+    imms: u8,
+    immr: u8
+}
+
+impl TryFrom<u64> for BitmaskImmediate {
+    type Error = ();
+
+    /// Attempt to convert a u64 into a BitmaskImmediate.
+    ///
+    /// The implementation here is largely based on this blog post:
+    /// <https://dougallj.wordpress.com/2021/10/30/bit-twiddling-optimising-aarch64-logical-immediate-encoding-and-decoding/>
+    fn try_from(value: u64) -> Result<Self, Self::Error> {
+        if value == 0 || value == u64::MAX {
+            return Err(());
+        }
+
+        fn rotate_right(value: u64, rotations: u32) -> u64 {
+            (value >> (rotations & 0x3F)) |
+            (value << (rotations.wrapping_neg() & 0x3F))
+        }
+
+        let rotations = (value & (value + 1)).trailing_zeros();
+        let normalized = rotate_right(value, rotations & 0x3F);
+
+        let zeroes = normalized.leading_zeros();
+        let ones = (!normalized).trailing_zeros();
+        let size = zeroes + ones;
+
+        if rotate_right(value, size & 0x3F) != value {
+            return Err(());
+        }
+
+        Ok(BitmaskImmediate {
+            n: ((size >> 6) & 1) as u8,
+            imms: (((size << 1).wrapping_neg() | (ones - 1)) & 0x3F) as u8,
+            immr: ((rotations.wrapping_neg() & (size - 1)) & 0x3F) as u8
+        })
+    }
+}
+
+impl BitmaskImmediate {
+    /// Attempt to make a BitmaskImmediate for a 32 bit register.
+    /// The result has N==0, which is required for some 32-bit instructions.
+    /// Note that the exact same BitmaskImmediate produces different values
+    /// depending on the size of the target register.
+    pub fn new_32b_reg(value: u32) -> Result<Self, ()> {
+        // The same bit pattern replicated to u64
+        let value = value as u64;
+        let replicated: u64 = (value << 32) | value;
+        let converted = Self::try_from(replicated);
+        if let Ok(ref imm) = converted {
+            assert_eq!(0, imm.n);
+        }
+
+        converted
+    }
+}
+
+impl BitmaskImmediate {
+    /// Encode a bitmask immediate into a 32-bit value.
+    pub fn encode(self) -> u32 {
+        0
+        | ((self.n as u32) << 12)
+        | ((self.immr as u32) << 6)
+        | (self.imms as u32)
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_failures() {
+        [5, 9, 10, 11, 13, 17, 18, 19].iter().for_each(|&imm| {
+            assert!(BitmaskImmediate::try_from(imm).is_err());
+        });
+    }
+
+    #[test]
+    fn test_negative() {
+        let bitmask: BitmaskImmediate = (-9_i64 as u64).try_into().unwrap();
+        let encoded: u32 = bitmask.encode();
+        assert_eq!(7998, encoded);
+    }
+
+    #[test]
+    fn test_size_2_minimum() {
+        let bitmask = BitmaskImmediate::try_from(0x5555555555555555);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000000, imms: 0b111100 })));
+    }
+
+    #[test]
+    fn test_size_2_maximum() {
+        let bitmask = BitmaskImmediate::try_from(0xaaaaaaaaaaaaaaaa);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000001, imms: 0b111100 })));
+    }
+
+    #[test]
+    fn test_size_4_minimum() {
+        let bitmask = BitmaskImmediate::try_from(0x1111111111111111);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000000, imms: 0b111000 })));
+    }
+
+    #[test]
+    fn test_size_4_rotated() {
+        let bitmask = BitmaskImmediate::try_from(0x6666666666666666);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000011, imms: 0b111001 })));
+    }
+
+    #[test]
+    fn test_size_4_maximum() {
+        let bitmask = BitmaskImmediate::try_from(0xeeeeeeeeeeeeeeee);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000011, imms: 0b111010 })));
+    }
+
+    #[test]
+    fn test_size_8_minimum() {
+        let bitmask = BitmaskImmediate::try_from(0x0101010101010101);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000000, imms: 0b110000 })));
+    }
+
+    #[test]
+    fn test_size_8_rotated() {
+        let bitmask = BitmaskImmediate::try_from(0x1818181818181818);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000101, imms: 0b110001 })));
+    }
+
+    #[test]
+    fn test_size_8_maximum() {
+        let bitmask = BitmaskImmediate::try_from(0xfefefefefefefefe);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000111, imms: 0b110110 })));
+    }
+
+    #[test]
+    fn test_size_16_minimum() {
+        let bitmask = BitmaskImmediate::try_from(0x0001000100010001);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000000, imms: 0b100000 })));
+    }
+
+    #[test]
+    fn test_size_16_rotated() {
+        let bitmask = BitmaskImmediate::try_from(0xff8fff8fff8fff8f);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b001001, imms: 0b101100 })));
+    }
+
+    #[test]
+    fn test_size_16_maximum() {
+        let bitmask = BitmaskImmediate::try_from(0xfffefffefffefffe);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b001111, imms: 0b101110 })));
+    }
+
+    #[test]
+    fn test_size_32_minimum() {
+        let bitmask = BitmaskImmediate::try_from(0x0000000100000001);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b000000, imms: 0b000000 })));
+    }
+
+    #[test]
+    fn test_size_32_rotated() {
+        let bitmask = BitmaskImmediate::try_from(0x3fffff003fffff00);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b011000, imms: 0b010101 })));
+    }
+
+    #[test]
+    fn test_size_32_maximum() {
+        let bitmask = BitmaskImmediate::try_from(0xfffffffefffffffe);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 0, immr: 0b011111, imms: 0b011110 })));
+    }
+
+    #[test]
+    fn test_size_64_minimum() {
+        let bitmask = BitmaskImmediate::try_from(0x0000000000000001);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 1, immr: 0b000000, imms: 0b000000 })));
+    }
+
+    #[test]
+    fn test_size_64_rotated() {
+        let bitmask = BitmaskImmediate::try_from(0x0000001fffff0000);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 1, immr: 0b110000, imms: 0b010100 })));
+    }
+
+    #[test]
+    fn test_size_64_maximum() {
+        let bitmask = BitmaskImmediate::try_from(0xfffffffffffffffe);
+        assert!(matches!(bitmask, Ok(BitmaskImmediate { n: 1, immr: 0b111111, imms: 0b111110 })));
+    }
+
+    #[test]
+    fn test_size_64_invalid() {
+        let bitmask = BitmaskImmediate::try_from(u64::MAX);
+        assert!(matches!(bitmask, Err(())));
+    }
+
+    #[test]
+    fn test_all_valid_32b_pattern() {
+        let mut patterns = vec![];
+        for pattern_size in [2, 4, 8, 16, 32_u64] {
+            for ones_count in 1..pattern_size {
+                for rotation in 0..pattern_size {
+                    let ones = (1_u64 << ones_count) - 1;
+                    let rotated = (ones >> rotation) |
+                        ((ones & ((1 << rotation) - 1)) << (pattern_size - rotation));
+                    let mut replicated = rotated;
+                    let mut shift = pattern_size;
+                    while shift < 32 {
+                        replicated |= replicated << shift;
+                        shift *= 2;
+                    }
+                    let replicated: u32 = replicated.try_into().unwrap();
+                    assert!(BitmaskImmediate::new_32b_reg(replicated).is_ok());
+                    patterns.push(replicated);
+                }
+            }
+        }
+        patterns.sort();
+        patterns.dedup();
+        // Up to {size}-1 ones, and a total of {size} possible rotations.
+        assert_eq!(1*2 + 3*4 + 7*8 + 15*16 + 31*32, patterns.len());
+    }
+}
diff --git a/zjit/src/asm/arm64/arg/condition.rs b/zjit/src/asm/arm64/arg/condition.rs
new file mode 100644
index 0000000000..f711b8b0d8
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/condition.rs
@@ -0,0 +1,52 @@
+/// Various instructions in A64 can have condition codes attached. This enum
+/// includes all of the various kinds of conditions along with their respective
+/// encodings.
+pub struct Condition;
+
+impl Condition {
+    pub const EQ: u8 = 0b0000; // equal to
+    pub const NE: u8 = 0b0001; // not equal to
+    pub const CS: u8 = 0b0010; // carry set (alias for HS)
+    pub const CC: u8 = 0b0011; // carry clear (alias for LO)
+    pub const MI: u8 = 0b0100; // minus, negative
+    pub const PL: u8 = 0b0101; // positive or zero
+    pub const VS: u8 = 0b0110; // signed overflow
+    pub const VC: u8 = 0b0111; // no signed overflow
+    pub const HI: u8 = 0b1000; // greater than (unsigned)
+    pub const LS: u8 = 0b1001; // less than or equal to (unsigned)
+    pub const GE: u8 = 0b1010; // greater than or equal to (signed)
+    pub const LT: u8 = 0b1011; // less than (signed)
+    pub const GT: u8 = 0b1100; // greater than (signed)
+    pub const LE: u8 = 0b1101; // less than or equal to (signed)
+    pub const AL: u8 = 0b1110; // always
+
+    pub const fn inverse(condition: u8) -> u8 {
+        match condition {
+            Condition::EQ => Condition::NE,
+            Condition::NE => Condition::EQ,
+
+            Condition::CS => Condition::CC,
+            Condition::CC => Condition::CS,
+
+            Condition::MI => Condition::PL,
+            Condition::PL => Condition::MI,
+
+            Condition::VS => Condition::VC,
+            Condition::VC => Condition::VS,
+
+            Condition::HI => Condition::LS,
+            Condition::LS => Condition::HI,
+
+            Condition::LT => Condition::GE,
+            Condition::GE => Condition::LT,
+
+            Condition::GT => Condition::LE,
+            Condition::LE => Condition::GT,
+
+            Condition::AL => Condition::AL,
+
+            _ => panic!("Unknown condition")
+
+        }
+    }
+}
diff --git a/zjit/src/asm/arm64/arg/inst_offset.rs b/zjit/src/asm/arm64/arg/inst_offset.rs
new file mode 100644
index 0000000000..f4a6bc73a0
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/inst_offset.rs
@@ -0,0 +1,47 @@
+/// There are a lot of instructions in the AArch64 architectrue that take an
+/// offset in terms of number of instructions. Usually they are jump
+/// instructions or instructions that load a value relative to the current PC.
+///
+/// This struct is used to mark those locations instead of a generic operand in
+/// order to give better clarity to the developer when reading the AArch64
+/// backend code. It also helps to clarify that everything is in terms of a
+/// number of instructions and not a number of bytes (i.e., the offset is the
+/// number of bytes divided by 4).
+#[derive(Copy, Clone)]
+pub struct InstructionOffset(i32);
+
+impl InstructionOffset {
+    /// Create a new instruction offset.
+    pub fn from_insns(insns: i32) -> Self {
+        InstructionOffset(insns)
+    }
+
+    /// Create a new instruction offset from a number of bytes.
+    pub fn from_bytes(bytes: i32) -> Self {
+        assert_eq!(bytes % 4, 0, "Byte offset must be a multiple of 4");
+        InstructionOffset(bytes / 4)
+    }
+}
+
+impl From<i32> for InstructionOffset {
+    /// Convert an i64 into an instruction offset.
+    fn from(value: i32) -> Self {
+        InstructionOffset(value)
+    }
+}
+
+impl From<InstructionOffset> for i32 {
+    /// Convert an instruction offset into a number of instructions as an i32.
+    fn from(offset: InstructionOffset) -> Self {
+        offset.0
+    }
+}
+
+impl From<InstructionOffset> for i64 {
+    /// Convert an instruction offset into a number of instructions as an i64.
+    /// This is useful for when we're checking how many bits this offset fits
+    /// into.
+    fn from(offset: InstructionOffset) -> Self {
+        offset.0.into()
+    }
+}
diff --git a/zjit/src/asm/arm64/arg/mod.rs b/zjit/src/asm/arm64/arg/mod.rs
new file mode 100644
index 0000000000..7eb37834f9
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/mod.rs
@@ -0,0 +1,18 @@
+// This module contains various A64 instruction arguments and the logic
+// necessary to encode them.
+
+mod bitmask_imm;
+mod condition;
+mod inst_offset;
+mod sf;
+mod shifted_imm;
+mod sys_reg;
+mod truncate;
+
+pub use bitmask_imm::BitmaskImmediate;
+pub use condition::Condition;
+pub use inst_offset::InstructionOffset;
+pub use sf::Sf;
+pub use shifted_imm::ShiftedImmediate;
+pub use sys_reg::SystemRegister;
+pub use truncate::{truncate_imm, truncate_uimm};
diff --git a/zjit/src/asm/arm64/arg/sf.rs b/zjit/src/asm/arm64/arg/sf.rs
new file mode 100644
index 0000000000..b6091821e9
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/sf.rs
@@ -0,0 +1,19 @@
+/// This is commonly the top-most bit in the encoding of the instruction, and
+/// represents whether register operands should be treated as 64-bit registers
+/// or 32-bit registers.
+pub enum Sf {
+    Sf32 = 0b0,
+    Sf64 = 0b1
+}
+
+/// A convenience function so that we can convert the number of bits of an
+/// register operand directly into an Sf enum variant.
+impl From<u8> for Sf {
+    fn from(num_bits: u8) -> Self {
+        match num_bits {
+            64 => Sf::Sf64,
+            32 => Sf::Sf32,
+            _ => panic!("Invalid number of bits: {num_bits}"),
+        }
+    }
+}
diff --git a/zjit/src/asm/arm64/arg/shifted_imm.rs b/zjit/src/asm/arm64/arg/shifted_imm.rs
new file mode 100644
index 0000000000..06daefdef7
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/shifted_imm.rs
@@ -0,0 +1,80 @@
+/// How much to shift the immediate by.
+pub enum Shift {
+    LSL0 = 0b0, // no shift
+    LSL12 = 0b1 // logical shift left by 12 bits
+}
+
+/// Some instructions accept a 12-bit immediate that has an optional shift
+/// attached to it. This allows encoding larger values than just fit into 12
+/// bits. We attempt to encode those here. If the values are too large we have
+/// to bail out.
+pub struct ShiftedImmediate {
+    shift: Shift,
+    value: u16
+}
+
+impl TryFrom<u64> for ShiftedImmediate {
+    type Error = ();
+
+    fn try_from(value: u64) -> Result<Self, Self::Error> {
+        let current = value;
+        if current < 2_u64.pow(12) {
+            return Ok(ShiftedImmediate { shift: Shift::LSL0, value: current as u16 });
+        }
+
+        if (current & (2_u64.pow(12) - 1) == 0) && ((current >> 12) < 2_u64.pow(12)) {
+            return Ok(ShiftedImmediate { shift: Shift::LSL12, value: (current >> 12) as u16 });
+        }
+
+        Err(())
+    }
+}
+
+impl From<ShiftedImmediate> for u32 {
+    /// Encode a bitmask immediate into a 32-bit value.
+    fn from(imm: ShiftedImmediate) -> Self {
+        0
+        | (((imm.shift as u32) & 1) << 12)
+        | (imm.value as u32)
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_no_shift() {
+        let expected_value = 256;
+        let result = ShiftedImmediate::try_from(expected_value);
+
+        match result {
+            Ok(ShiftedImmediate { shift: Shift::LSL0, value }) => assert_eq!(value as u64, expected_value),
+            _ => panic!("Unexpected shift value")
+        }
+    }
+
+    #[test]
+    fn test_maximum_no_shift() {
+        let expected_value = (1 << 12) - 1;
+        let result = ShiftedImmediate::try_from(expected_value);
+
+        match result {
+            Ok(ShiftedImmediate { shift: Shift::LSL0, value }) => assert_eq!(value as u64, expected_value),
+            _ => panic!("Unexpected shift value")
+        }
+    }
+
+    #[test]
+    fn test_with_shift() {
+        let result = ShiftedImmediate::try_from(256 << 12);
+
+        assert!(matches!(result, Ok(ShiftedImmediate { shift: Shift::LSL12, value: 256 })));
+    }
+
+    #[test]
+    fn test_unencodable() {
+        let result = ShiftedImmediate::try_from((256 << 12) + 1);
+        assert!(matches!(result, Err(())));
+    }
+}
diff --git a/zjit/src/asm/arm64/arg/sys_reg.rs b/zjit/src/asm/arm64/arg/sys_reg.rs
new file mode 100644
index 0000000000..6229d5c1fd
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/sys_reg.rs
@@ -0,0 +1,6 @@
+/// The encoded representation of an A64 system register.
+/// <https://developer.arm.com/documentation/ddi0601/2022-06/AArch64-Registers/>
+pub enum SystemRegister {
+    /// <https://developer.arm.com/documentation/ddi0601/2022-06/AArch64-Registers/NZCV--Condition-Flags?lang=en>
+    NZCV = 0b1_011_0100_0010_000
+}
diff --git a/zjit/src/asm/arm64/arg/truncate.rs b/zjit/src/asm/arm64/arg/truncate.rs
new file mode 100644
index 0000000000..85d56ff202
--- /dev/null
+++ b/zjit/src/asm/arm64/arg/truncate.rs
@@ -0,0 +1,66 @@
+// There are many instances in AArch64 instruction encoding where you represent
+// an integer value with a particular bit width that isn't a power of 2. These
+// functions represent truncating those integer values down to the appropriate
+// number of bits.
+
+/// Truncate a signed immediate to fit into a compile-time known width. It is
+/// assumed before calling this function that the value fits into the correct
+/// size. If it doesn't, then this function will panic.
+///
+/// When the value is positive, this should effectively be a no-op since we're
+/// just dropping leading zeroes. When the value is negative we should only be
+/// dropping leading ones.
+pub fn truncate_imm<T: Into<i32>, const WIDTH: usize>(imm: T) -> u32 {
+    let value: i32 = imm.into();
+    let masked = (value as u32) & ((1 << WIDTH) - 1);
+
+    // Assert that we didn't drop any bits by truncating.
+    if value >= 0 {
+        assert_eq!(value as u32, masked);
+    } else {
+        assert_eq!(value as u32, masked | (u32::MAX << WIDTH));
+    }
+
+    masked
+}
+
+/// Truncate an unsigned immediate to fit into a compile-time known width. It is
+/// assumed before calling this function that the value fits into the correct
+/// size. If it doesn't, then this function will panic.
+///
+/// This should effectively be a no-op since we're just dropping leading zeroes.
+pub fn truncate_uimm<T: Into<u32>, const WIDTH: usize>(uimm: T) -> u32 {
+    let value: u32 = uimm.into();
+    let masked = value & ((1 << WIDTH) - 1);
+
+    // Assert that we didn't drop any bits by truncating.
+    assert_eq!(value, masked);
+
+    masked
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_truncate_imm_positive() {
+        let inst = truncate_imm::<i32, 4>(5);
+        let result: u32 = inst;
+        assert_eq!(0b0101, result);
+    }
+
+    #[test]
+    fn test_truncate_imm_negative() {
+        let inst = truncate_imm::<i32, 4>(-5);
+        let result: u32 = inst;
+        assert_eq!(0b1011, result);
+    }
+
+    #[test]
+    fn test_truncate_uimm() {
+        let inst = truncate_uimm::<u32, 4>(5);
+        let result: u32 = inst;
+        assert_eq!(0b0101, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/atomic.rs b/zjit/src/asm/arm64/inst/atomic.rs
new file mode 100644
index 0000000000..0917a4fd1c
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/atomic.rs
@@ -0,0 +1,86 @@
+/// The size of the register operands to this instruction.
+enum Size {
+    /// Using 32-bit registers.
+    Size32 = 0b10,
+
+    /// Using 64-bit registers.
+    Size64 = 0b11
+}
+
+/// A convenience function so that we can convert the number of bits of an
+/// register operand directly into a Size enum variant.
+impl From<u8> for Size {
+    fn from(num_bits: u8) -> Self {
+        match num_bits {
+            64 => Size::Size64,
+            32 => Size::Size32,
+            _ => panic!("Invalid number of bits: {num_bits}"),
+        }
+    }
+}
+
+/// The struct that represents an A64 atomic instruction that can be encoded.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |        1  1    1  0  0  0    1  1  1                     0  0  0  0    0  0                                   |
+/// | size                                 rs..............                       rn.............. rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct Atomic {
+    /// The register holding the value to be loaded.
+    rt: u8,
+
+    /// The base register.
+    rn: u8,
+
+    /// The register holding the data value to be operated on.
+    rs: u8,
+
+    /// The size of the registers used in this instruction.
+    size: Size
+}
+
+impl Atomic {
+    /// LDADDAL
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDADD--LDADDA--LDADDAL--LDADDL--Atomic-add-on-word-or-doubleword-in-memory-?lang=en>
+    pub fn ldaddal(rs: u8, rt: u8, rn: u8, num_bits: u8) -> Self {
+        Self { rt, rn, rs, size: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en>
+const FAMILY: u32 = 0b0100;
+
+impl From<Atomic> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: Atomic) -> Self {
+        0
+        | ((inst.size as u32) << 30)
+        | (0b11 << 28)
+        | (FAMILY << 25)
+        | (0b111 << 21)
+        | ((inst.rs as u32) << 16)
+        | ((inst.rn as u32) << 5)
+        | (inst.rt as u32)
+    }
+}
+
+impl From<Atomic> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: Atomic) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_ldaddal() {
+        let result: u32 = Atomic::ldaddal(20, 21, 22, 64).into();
+        assert_eq!(0xf8f402d5, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/branch.rs b/zjit/src/asm/arm64/inst/branch.rs
new file mode 100644
index 0000000000..2db52e5d31
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/branch.rs
@@ -0,0 +1,100 @@
+/// Which operation to perform.
+enum Op {
+    /// Perform a BR instruction.
+    BR = 0b00,
+
+    /// Perform a BLR instruction.
+    BLR = 0b01,
+
+    /// Perform a RET instruction.
+    RET = 0b10
+}
+
+/// The struct that represents an A64 branch instruction that can be encoded.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  1  1  0  1    0  1  1  0    0        1    1  1  1  1    0  0  0  0    0  0                   0    0  0  0  0 |
+/// |                                op...                                        rn.............. rm.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct Branch {
+    /// The register holding the address to be branched to.
+    rn: u8,
+
+    /// The operation to perform.
+    op: Op
+}
+
+impl Branch {
+    /// BR
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/BR--Branch-to-Register-?lang=en>
+    pub fn br(rn: u8) -> Self {
+        Self { rn, op: Op::BR }
+    }
+
+    /// BLR
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/BLR--Branch-with-Link-to-Register-?lang=en>
+    pub fn blr(rn: u8) -> Self {
+        Self { rn, op: Op::BLR }
+    }
+
+    /// RET
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/RET--Return-from-subroutine-?lang=en>
+    pub fn ret(rn: u8) -> Self {
+        Self { rn, op: Op::RET }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions?lang=en>
+const FAMILY: u32 = 0b101;
+
+impl From<Branch> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: Branch) -> Self {
+        0
+        | (0b11 << 30)
+        | (FAMILY << 26)
+        | (1 << 25)
+        | ((inst.op as u32) << 21)
+        | (0b11111 << 16)
+        | ((inst.rn as u32) << 5)
+    }
+}
+
+impl From<Branch> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: Branch) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_br() {
+        let result: u32 = Branch::br(0).into();
+        assert_eq!(0xd61f0000, result);
+    }
+
+    #[test]
+    fn test_blr() {
+        let result: u32 = Branch::blr(0).into();
+        assert_eq!(0xd63f0000, result);
+    }
+
+    #[test]
+    fn test_ret() {
+        let result: u32 = Branch::ret(30).into();
+        assert_eq!(0xd65f03c0, result);
+    }
+
+    #[test]
+    fn test_ret_rn() {
+        let result: u32 = Branch::ret(20).into();
+        assert_eq!(0xd65f0280, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/branch_cond.rs b/zjit/src/asm/arm64/inst/branch_cond.rs
new file mode 100644
index 0000000000..266e9ccb31
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/branch_cond.rs
@@ -0,0 +1,78 @@
+use super::super::arg::{InstructionOffset, truncate_imm};
+
+/// The struct that represents an A64 conditional branch instruction that can be
+/// encoded.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  0  1  0  1    0  1  0  0                                                                     0               |
+/// |                             imm19...........................................................      cond....... |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct BranchCond {
+    /// The kind of condition to check before branching.
+    cond: u8,
+
+    /// The instruction offset from this instruction to branch to.
+    offset: InstructionOffset
+}
+
+impl BranchCond {
+    /// B.cond
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/B-cond--Branch-conditionally->
+    pub fn bcond(cond: u8, offset: InstructionOffset) -> Self {
+        Self { cond, offset }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions?lang=en>
+const FAMILY: u32 = 0b101;
+
+impl From<BranchCond> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: BranchCond) -> Self {
+        0
+        | (1 << 30)
+        | (FAMILY << 26)
+        | (truncate_imm::<_, 19>(inst.offset) << 5)
+        | (inst.cond as u32)
+    }
+}
+
+impl From<BranchCond> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: BranchCond) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use super::super::super::arg::Condition;
+
+    #[test]
+    fn test_b_eq() {
+        let result: u32 = BranchCond::bcond(Condition::EQ, 32.into()).into();
+        assert_eq!(0x54000400, result);
+    }
+
+    #[test]
+    fn test_b_vs() {
+        let result: u32 = BranchCond::bcond(Condition::VS, 32.into()).into();
+        assert_eq!(0x54000406, result);
+    }
+
+    #[test]
+    fn test_b_eq_max() {
+        let result: u32 = BranchCond::bcond(Condition::EQ, ((1 << 18) - 1).into()).into();
+        assert_eq!(0x547fffe0, result);
+    }
+
+    #[test]
+    fn test_b_eq_min() {
+        let result: u32 = BranchCond::bcond(Condition::EQ, (-(1 << 18)).into()).into();
+        assert_eq!(0x54800000, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/breakpoint.rs b/zjit/src/asm/arm64/inst/breakpoint.rs
new file mode 100644
index 0000000000..d66a35c4c6
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/breakpoint.rs
@@ -0,0 +1,55 @@
+/// The struct that represents an A64 breakpoint instruction that can be encoded.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  1  1  0  1    0  1  0  0    0  0  1                                                          0    0  0  0  0 |
+/// |                                      imm16..................................................                  |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct Breakpoint {
+    /// The value to be captured by ESR_ELx.ISS
+    imm16: u16
+}
+
+impl Breakpoint {
+    /// BRK
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/BRK--Breakpoint-instruction->
+    pub fn brk(imm16: u16) -> Self {
+        Self { imm16 }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions?lang=en#control>
+const FAMILY: u32 = 0b101;
+
+impl From<Breakpoint> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: Breakpoint) -> Self {
+        let imm16 = inst.imm16 as u32;
+
+        0
+        | (0b11 << 30)
+        | (FAMILY << 26)
+        | (1 << 21)
+        | (imm16 << 5)
+    }
+}
+
+impl From<Breakpoint> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: Breakpoint) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_brk() {
+        let result: u32 = Breakpoint::brk(7).into();
+        assert_eq!(0xd42000e0, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/call.rs b/zjit/src/asm/arm64/inst/call.rs
new file mode 100644
index 0000000000..fd26d09f8a
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/call.rs
@@ -0,0 +1,104 @@
+use super::super::arg::{InstructionOffset, truncate_imm};
+
+/// The operation to perform for this instruction.
+enum Op {
+    /// Branch directly, with a hint that this is not a subroutine call or
+    /// return.
+    Branch = 0,
+
+    /// Branch directly, with a hint that this is a subroutine call or return.
+    BranchWithLink = 1
+}
+
+/// The struct that represents an A64 branch with our without link instruction
+/// that can be encoded.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |     0  0  1    0  1                                                                                           |
+/// | op                  imm26.................................................................................... |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct Call {
+    /// The PC-relative offset to jump to in terms of number of instructions.
+    offset: InstructionOffset,
+
+    /// The operation to perform for this instruction.
+    op: Op
+}
+
+impl Call {
+    /// B
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/B--Branch->
+    pub fn b(offset: InstructionOffset) -> Self {
+        Self { offset, op: Op::Branch }
+    }
+
+    /// BL
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/BL--Branch-with-Link-?lang=en>
+    pub fn bl(offset: InstructionOffset) -> Self {
+        Self { offset, op: Op::BranchWithLink }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions?lang=en>
+const FAMILY: u32 = 0b101;
+
+impl From<Call> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: Call) -> Self {
+        0
+        | ((inst.op as u32) << 31)
+        | (FAMILY << 26)
+        | truncate_imm::<_, 26>(inst.offset)
+    }
+}
+
+impl From<Call> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: Call) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_bl() {
+        let result: u32 = Call::bl(0.into()).into();
+        assert_eq!(0x94000000, result);
+    }
+
+    #[test]
+    fn test_bl_positive() {
+        let result: u32 = Call::bl(256.into()).into();
+        assert_eq!(0x94000100, result);
+    }
+
+    #[test]
+    fn test_bl_negative() {
+        let result: u32 = Call::bl((-256).into()).into();
+        assert_eq!(0x97ffff00, result);
+    }
+
+    #[test]
+    fn test_b() {
+        let result: u32 = Call::b(0.into()).into();
+        assert_eq!(0x14000000, result);
+    }
+
+    #[test]
+    fn test_b_positive() {
+        let result: u32 = Call::b(((1 << 25) - 1).into()).into();
+        assert_eq!(0x15ffffff, result);
+    }
+
+    #[test]
+    fn test_b_negative() {
+        let result: u32 = Call::b((-(1 << 25)).into()).into();
+        assert_eq!(0x16000000, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/conditional.rs b/zjit/src/asm/arm64/inst/conditional.rs
new file mode 100644
index 0000000000..1e26c7408b
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/conditional.rs
@@ -0,0 +1,73 @@
+use super::super::arg::Sf;
+
+/// The struct that represents an A64 conditional instruction that can be
+/// encoded.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |     0  0  1    1  0  1  0    1  0  0                                   0  0                                   |
+/// | sf                                   rm..............   cond.......         rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct Conditional {
+    /// The number of the general-purpose destination register.
+    rd: u8,
+
+    /// The number of the first general-purpose source register.
+    rn: u8,
+
+    /// The condition to use for the conditional instruction.
+    cond: u8,
+
+    /// The number of the second general-purpose source register.
+    rm: u8,
+
+    /// The size of the registers of this instruction.
+    sf: Sf
+}
+
+impl Conditional {
+    /// CSEL
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CSEL--Conditional-Select-?lang=en>
+    pub fn csel(rd: u8, rn: u8, rm: u8, cond: u8, num_bits: u8) -> Self {
+        Self { rd, rn, cond, rm, sf: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Register?lang=en#condsel>
+const FAMILY: u32 = 0b101;
+
+impl From<Conditional> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: Conditional) -> Self {
+        0
+        | ((inst.sf as u32) << 31)
+        | (1 << 28)
+        | (FAMILY << 25)
+        | (1 << 23)
+        | ((inst.rm as u32) << 16)
+        | ((inst.cond as u32) << 12)
+        | ((inst.rn as u32) << 5)
+        | (inst.rd as u32)
+    }
+}
+
+impl From<Conditional> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: Conditional) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use super::super::super::arg::Condition;
+
+    #[test]
+    fn test_csel() {
+        let result: u32 = Conditional::csel(0, 1, 2, Condition::NE, 64).into();
+        assert_eq!(0x9a821020, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/data_imm.rs b/zjit/src/asm/arm64/inst/data_imm.rs
new file mode 100644
index 0000000000..ea71705478
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/data_imm.rs
@@ -0,0 +1,143 @@
+use super::super::arg::{Sf, ShiftedImmediate};
+
+/// The operation being performed by this instruction.
+enum Op {
+    Add = 0b0,
+    Sub = 0b1
+}
+
+// Whether or not to update the flags when this instruction is performed.
+enum S {
+    LeaveFlags = 0b0,
+    UpdateFlags = 0b1
+}
+
+/// The struct that represents an A64 data processing -- immediate instruction
+/// that can be encoded.
+///
+/// Add/subtract (immediate)
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |           1    0  0  0  1    0                                                                                |
+/// | sf op  S                       sh imm12.................................... rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct DataImm {
+    /// The register number of the destination register.
+    rd: u8,
+
+    /// The register number of the first operand register.
+    rn: u8,
+
+    /// How much to shift the immediate by.
+    imm: ShiftedImmediate,
+
+    /// Whether or not to update the flags when this instruction is performed.
+    s: S,
+
+    /// The opcode for this instruction.
+    op: Op,
+
+    /// Whether or not this instruction is operating on 64-bit operands.
+    sf: Sf
+}
+
+impl DataImm {
+    /// ADD (immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADD--immediate---Add--immediate--?lang=en>
+    pub fn add(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, s: S::LeaveFlags, op: Op::Add, sf: num_bits.into() }
+    }
+
+    /// ADDS (immediate, set flags)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADDS--immediate---Add--immediate---setting-flags-?lang=en>
+    pub fn adds(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, s: S::UpdateFlags, op: Op::Add, sf: num_bits.into() }
+    }
+
+    /// CMP (immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CMP--immediate---Compare--immediate---an-alias-of-SUBS--immediate--?lang=en>
+    pub fn cmp(rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
+        Self::subs(31, rn, imm, num_bits)
+    }
+
+    /// SUB (immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUB--immediate---Subtract--immediate--?lang=en>
+    pub fn sub(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, s: S::LeaveFlags, op: Op::Sub, sf: num_bits.into() }
+    }
+
+    /// SUBS (immediate, set flags)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUBS--immediate---Subtract--immediate---setting-flags-?lang=en>
+    pub fn subs(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, s: S::UpdateFlags, op: Op::Sub, sf: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Immediate?lang=en>
+const FAMILY: u32 = 0b1000;
+
+impl From<DataImm> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: DataImm) -> Self {
+        let imm: u32 = inst.imm.into();
+
+        0
+        | ((inst.sf as u32) << 31)
+        | ((inst.op as u32) << 30)
+        | ((inst.s as u32) << 29)
+        | (FAMILY << 25)
+        | (1 << 24)
+        | (imm << 10)
+        | ((inst.rn as u32) << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<DataImm> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: DataImm) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_add() {
+        let inst = DataImm::add(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x91001c20, result);
+    }
+
+    #[test]
+    fn test_adds() {
+        let inst = DataImm::adds(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xb1001c20, result);
+    }
+
+    #[test]
+    fn test_cmp() {
+        let inst = DataImm::cmp(0, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf1001c1f, result);
+    }
+
+    #[test]
+    fn test_sub() {
+        let inst = DataImm::sub(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd1001c20, result);
+    }
+
+    #[test]
+    fn test_subs() {
+        let inst = DataImm::subs(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf1001c20, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/data_reg.rs b/zjit/src/asm/arm64/inst/data_reg.rs
new file mode 100644
index 0000000000..ed4afa956b
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/data_reg.rs
@@ -0,0 +1,192 @@
+use super::super::arg::{Sf, truncate_uimm};
+
+/// The operation being performed by this instruction.
+enum Op {
+    Add = 0b0,
+    Sub = 0b1
+}
+
+// Whether or not to update the flags when this instruction is performed.
+enum S {
+    LeaveFlags = 0b0,
+    UpdateFlags = 0b1
+}
+
+/// The type of shift to perform on the second operand register.
+enum Shift {
+    LSL = 0b00, // logical shift left (unsigned)
+    LSR = 0b01, // logical shift right (unsigned)
+    ASR = 0b10  // arithmetic shift right (signed)
+}
+
+/// The struct that represents an A64 data processing -- register instruction
+/// that can be encoded.
+///
+/// Add/subtract (shifted register)
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |           0    1  0  1  1          0                                                                          |
+/// | sf op  S                    shift    rm..............   imm6............... rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct DataReg {
+    /// The register number of the destination register.
+    rd: u8,
+
+    /// The register number of the first operand register.
+    rn: u8,
+
+    /// The amount to shift the second operand register by.
+    imm6: u8,
+
+    /// The register number of the second operand register.
+    rm: u8,
+
+    /// The type of shift to perform on the second operand register.
+    shift: Shift,
+
+    /// Whether or not to update the flags when this instruction is performed.
+    s: S,
+
+    /// The opcode for this instruction.
+    op: Op,
+
+    /// Whether or not this instruction is operating on 64-bit operands.
+    sf: Sf
+}
+
+impl DataReg {
+    /// ADD (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADD--shifted-register---Add--shifted-register--?lang=en>
+    pub fn add(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self {
+            rd,
+            rn,
+            imm6: 0,
+            rm,
+            shift: Shift::LSL,
+            s: S::LeaveFlags,
+            op: Op::Add,
+            sf: num_bits.into()
+        }
+    }
+
+    /// ADDS (shifted register, set flags)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADDS--shifted-register---Add--shifted-register---setting-flags-?lang=en>
+    pub fn adds(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self {
+            rd,
+            rn,
+            imm6: 0,
+            rm,
+            shift: Shift::LSL,
+            s: S::UpdateFlags,
+            op: Op::Add,
+            sf: num_bits.into()
+        }
+    }
+
+    /// CMP (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CMP--shifted-register---Compare--shifted-register---an-alias-of-SUBS--shifted-register--?lang=en>
+    pub fn cmp(rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self::subs(31, rn, rm, num_bits)
+    }
+
+    /// SUB (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUB--shifted-register---Subtract--shifted-register--?lang=en>
+    pub fn sub(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self {
+            rd,
+            rn,
+            imm6: 0,
+            rm,
+            shift: Shift::LSL,
+            s: S::LeaveFlags,
+            op: Op::Sub,
+            sf: num_bits.into()
+        }
+    }
+
+    /// SUBS (shifted register, set flags)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUBS--shifted-register---Subtract--shifted-register---setting-flags-?lang=en>
+    pub fn subs(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self {
+            rd,
+            rn,
+            imm6: 0,
+            rm,
+            shift: Shift::LSL,
+            s: S::UpdateFlags,
+            op: Op::Sub,
+            sf: num_bits.into()
+        }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Register?lang=en>
+const FAMILY: u32 = 0b0101;
+
+impl From<DataReg> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: DataReg) -> Self {
+        0
+        | ((inst.sf as u32) << 31)
+        | ((inst.op as u32) << 30)
+        | ((inst.s as u32) << 29)
+        | (FAMILY << 25)
+        | (1 << 24)
+        | ((inst.shift as u32) << 22)
+        | ((inst.rm as u32) << 16)
+        | (truncate_uimm::<_, 6>(inst.imm6) << 10)
+        | ((inst.rn as u32) << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<DataReg> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: DataReg) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_add() {
+        let inst = DataReg::add(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x8b020020, result);
+    }
+
+    #[test]
+    fn test_adds() {
+        let inst = DataReg::adds(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xab020020, result);
+    }
+
+    #[test]
+    fn test_cmp() {
+        let inst = DataReg::cmp(0, 1, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xeb01001f, result);
+    }
+
+    #[test]
+    fn test_sub() {
+        let inst = DataReg::sub(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xcb020020, result);
+    }
+
+    #[test]
+    fn test_subs() {
+        let inst = DataReg::subs(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xeb020020, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/halfword_imm.rs b/zjit/src/asm/arm64/inst/halfword_imm.rs
new file mode 100644
index 0000000000..863ac947dd
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/halfword_imm.rs
@@ -0,0 +1,179 @@
+use super::super::arg::truncate_imm;
+
+/// Whether this is a load or a store.
+enum Op {
+    Load = 1,
+    Store = 0
+}
+
+/// The type of indexing to perform for this instruction.
+enum Index {
+    /// No indexing.
+    None = 0b00,
+
+    /// Mutate the register after the read.
+    PostIndex = 0b01,
+
+    /// Mutate the register before the read.
+    PreIndex = 0b11
+}
+
+/// The struct that represents an A64 halfword instruction that can be encoded.
+///
+/// LDRH/STRH
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  0  1  1  1    1  0  0  1    0                                                                                |
+/// |                                op imm12.................................... rn.............. rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+/// LDRH (pre-index/post-index)
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  0  1  1  1    1  0  0  0    0     0                                                                          |
+/// |                                op    imm9..........................   index rn.............. rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct HalfwordImm {
+    /// The number of the 32-bit register to be loaded.
+    rt: u8,
+
+    /// The number of the 64-bit base register to calculate the memory address.
+    rn: u8,
+
+    /// The type of indexing to perform for this instruction.
+    index: Index,
+
+    /// The immediate offset from the base register.
+    imm: i16,
+
+    /// The operation to perform.
+    op: Op
+}
+
+impl HalfwordImm {
+    /// LDRH
+    /// <https://developer.arm.com/documentation/ddi0602/2022-06/Base-Instructions/LDRH--immediate---Load-Register-Halfword--immediate-->
+    pub fn ldrh(rt: u8, rn: u8, imm12: i16) -> Self {
+        Self { rt, rn, index: Index::None, imm: imm12, op: Op::Load }
+    }
+
+    /// LDRH (pre-index)
+    /// <https://developer.arm.com/documentation/ddi0602/2022-06/Base-Instructions/LDRH--immediate---Load-Register-Halfword--immediate-->
+    pub fn ldrh_pre(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, index: Index::PreIndex, imm: imm9, op: Op::Load }
+    }
+
+    /// LDRH (post-index)
+    /// <https://developer.arm.com/documentation/ddi0602/2022-06/Base-Instructions/LDRH--immediate---Load-Register-Halfword--immediate-->
+    pub fn ldrh_post(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, index: Index::PostIndex, imm: imm9, op: Op::Load }
+    }
+
+    /// STRH
+    /// <https://developer.arm.com/documentation/ddi0602/2022-06/Base-Instructions/STRH--immediate---Store-Register-Halfword--immediate-->
+    pub fn strh(rt: u8, rn: u8, imm12: i16) -> Self {
+        Self { rt, rn, index: Index::None, imm: imm12, op: Op::Store }
+    }
+
+    /// STRH (pre-index)
+    /// <https://developer.arm.com/documentation/ddi0602/2022-06/Base-Instructions/STRH--immediate---Store-Register-Halfword--immediate-->
+    pub fn strh_pre(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, index: Index::PreIndex, imm: imm9, op: Op::Store }
+    }
+
+    /// STRH (post-index)
+    /// <https://developer.arm.com/documentation/ddi0602/2022-06/Base-Instructions/STRH--immediate---Store-Register-Halfword--immediate-->
+    pub fn strh_post(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, index: Index::PostIndex, imm: imm9, op: Op::Store }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en>
+const FAMILY: u32 = 0b111100;
+
+impl From<HalfwordImm> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: HalfwordImm) -> Self {
+        let (opc, imm) = match inst.index {
+            Index::None => {
+                assert_eq!(inst.imm & 1, 0, "immediate offset must be even");
+                let imm12 = truncate_imm::<_, 12>(inst.imm / 2);
+                (0b100, imm12)
+            },
+            Index::PreIndex | Index::PostIndex => {
+                let imm9 = truncate_imm::<_, 9>(inst.imm);
+                (0b000, (imm9 << 2) | (inst.index as u32))
+            }
+        };
+
+        0
+        | (FAMILY << 25)
+        | ((opc | (inst.op as u32)) << 22)
+        | (imm << 10)
+        | ((inst.rn as u32) << 5)
+        | (inst.rt as u32)
+    }
+}
+
+impl From<HalfwordImm> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: HalfwordImm) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_ldrh() {
+        let inst = HalfwordImm::ldrh(0, 1, 8);
+        let result: u32 = inst.into();
+        assert_eq!(0x79401020, result);
+    }
+
+    #[test]
+    fn test_ldrh_pre() {
+        let inst = HalfwordImm::ldrh_pre(0, 1, 16);
+        let result: u32 = inst.into();
+        assert_eq!(0x78410c20, result);
+    }
+
+    #[test]
+    fn test_ldrh_post() {
+        let inst = HalfwordImm::ldrh_post(0, 1, 24);
+        let result: u32 = inst.into();
+        assert_eq!(0x78418420, result);
+    }
+
+    #[test]
+    fn test_ldrh_post_negative() {
+        let inst = HalfwordImm::ldrh_post(0, 1, -24);
+        let result: u32 = inst.into();
+        assert_eq!(0x785e8420, result);
+    }
+
+    #[test]
+    fn test_strh() {
+        let inst = HalfwordImm::strh(0, 1, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0x79000020, result);
+    }
+
+    #[test]
+    fn test_strh_pre() {
+        let inst = HalfwordImm::strh_pre(0, 1, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0x78000c20, result);
+    }
+
+    #[test]
+    fn test_strh_post() {
+        let inst = HalfwordImm::strh_post(0, 1, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0x78000420, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/load_literal.rs b/zjit/src/asm/arm64/inst/load_literal.rs
new file mode 100644
index 0000000000..37b5f3c7a7
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/load_literal.rs
@@ -0,0 +1,91 @@
+#![allow(clippy::identity_op)]
+
+use super::super::arg::{InstructionOffset, truncate_imm};
+
+/// The size of the operands being operated on.
+enum Opc {
+    Size32 = 0b00,
+    Size64 = 0b01,
+}
+
+/// A convenience function so that we can convert the number of bits of an
+/// register operand directly into an Sf enum variant.
+impl From<u8> for Opc {
+    fn from(num_bits: u8) -> Self {
+        match num_bits {
+            64 => Opc::Size64,
+            32 => Opc::Size32,
+            _ => panic!("Invalid number of bits: {num_bits}"),
+        }
+    }
+}
+
+/// The struct that represents an A64 load literal instruction that can be encoded.
+///
+/// LDR
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |        0  1    1  0  0  0                                                                                     |
+/// | opc..                       imm19........................................................... rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct LoadLiteral {
+    /// The number of the register to load the value into.
+    rt: u8,
+
+    /// The PC-relative number of instructions to load the value from.
+    offset: InstructionOffset,
+
+    /// The size of the operands being operated on.
+    opc: Opc
+}
+
+impl LoadLiteral {
+    /// LDR (load literal)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--literal---Load-Register--literal--?lang=en>
+    pub fn ldr_literal(rt: u8, offset: InstructionOffset, num_bits: u8) -> Self {
+        Self { rt, offset, opc: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en>
+const FAMILY: u32 = 0b0100;
+
+impl From<LoadLiteral> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: LoadLiteral) -> Self {
+        0
+        | ((inst.opc as u32) << 30)
+        | (1 << 28)
+        | (FAMILY << 25)
+        | (truncate_imm::<_, 19>(inst.offset) << 5)
+        | (inst.rt as u32)
+    }
+}
+
+impl From<LoadLiteral> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: LoadLiteral) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_ldr_positive() {
+        let inst = LoadLiteral::ldr_literal(0, 5.into(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x580000a0, result);
+    }
+
+    #[test]
+    fn test_ldr_negative() {
+        let inst = LoadLiteral::ldr_literal(0, (-5).into(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x58ffff60, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/load_register.rs b/zjit/src/asm/arm64/inst/load_register.rs
new file mode 100644
index 0000000000..80813ffc87
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/load_register.rs
@@ -0,0 +1,108 @@
+/// Whether or not to shift the register.
+enum S {
+    Shift = 1,
+    NoShift = 0
+}
+
+/// The option for this instruction.
+enum Option {
+    UXTW = 0b010,
+    LSL = 0b011,
+    SXTW = 0b110,
+    SXTX = 0b111
+}
+
+/// The size of the operands of this instruction.
+enum Size {
+    Size32 = 0b10,
+    Size64 = 0b11
+}
+
+/// A convenience function so that we can convert the number of bits of an
+/// register operand directly into a Size enum variant.
+impl From<u8> for Size {
+    fn from(num_bits: u8) -> Self {
+        match num_bits {
+            64 => Size::Size64,
+            32 => Size::Size32,
+            _ => panic!("Invalid number of bits: {num_bits}"),
+        }
+    }
+}
+
+/// The struct that represents an A64 load instruction that can be encoded.
+///
+/// LDR
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |        1  1    1  0  0  0    0  1  1                                   1  0                                   |
+/// | size.                                rm..............   option.. S          rn.............. rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct LoadRegister {
+    /// The number of the register to load the value into.
+    rt: u8,
+
+    /// The base register with which to form the address.
+    rn: u8,
+
+    /// Whether or not to shift the value of the register.
+    s: S,
+
+    /// The option associated with this instruction that controls the shift.
+    option: Option,
+
+    /// The number of the offset register.
+    rm: u8,
+
+    /// The size of the operands.
+    size: Size
+}
+
+impl LoadRegister {
+    /// LDR
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en>
+    pub fn ldr(rt: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rt, rn, s: S::NoShift, option: Option::LSL, rm, size: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en>
+const FAMILY: u32 = 0b0100;
+
+impl From<LoadRegister> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: LoadRegister) -> Self {
+        0
+        | ((inst.size as u32) << 30)
+        | (0b11 << 28)
+        | (FAMILY << 25)
+        | (0b11 << 21)
+        | ((inst.rm as u32) << 16)
+        | ((inst.option as u32) << 13)
+        | ((inst.s as u32) << 12)
+        | (0b10 << 10)
+        | ((inst.rn as u32) << 5)
+        | (inst.rt as u32)
+    }
+}
+
+impl From<LoadRegister> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: LoadRegister) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_ldr() {
+        let inst = LoadRegister::ldr(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf8626820, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/load_store.rs b/zjit/src/asm/arm64/inst/load_store.rs
new file mode 100644
index 0000000000..d38e851ed7
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/load_store.rs
@@ -0,0 +1,255 @@
+use super::super::arg::truncate_imm;
+
+/// The size of the operands being operated on.
+enum Size {
+    Size8 = 0b00,
+    Size16 = 0b01,
+    Size32 = 0b10,
+    Size64 = 0b11,
+}
+
+/// A convenience function so that we can convert the number of bits of an
+/// register operand directly into an Sf enum variant.
+impl From<u8> for Size {
+    fn from(num_bits: u8) -> Self {
+        match num_bits {
+            64 => Size::Size64,
+            32 => Size::Size32,
+            _ => panic!("Invalid number of bits: {num_bits}"),
+        }
+    }
+}
+
+/// The operation to perform for this instruction.
+enum Opc {
+    STR = 0b00,
+    LDR = 0b01,
+    LDURSW = 0b10
+}
+
+/// What kind of indexing to perform for this instruction.
+enum Index {
+    None = 0b00,
+    PostIndex = 0b01,
+    PreIndex = 0b11
+}
+
+/// The struct that represents an A64 load or store instruction that can be
+/// encoded.
+///
+/// LDR/LDUR/LDURSW/STR/STUR
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |        1  1    1  0  0  0          0                                                                          |
+/// | size.                       opc..    imm9..........................   idx.. rn.............. rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct LoadStore {
+    /// The number of the register to load the value into.
+    rt: u8,
+
+    /// The base register with which to form the address.
+    rn: u8,
+
+    /// What kind of indexing to perform for this instruction.
+    idx: Index,
+
+    /// The optional signed immediate byte offset from the base register.
+    imm9: i16,
+
+    /// The operation to perform for this instruction.
+    opc: Opc,
+
+    /// The size of the operands being operated on.
+    size: Size
+}
+
+impl LoadStore {
+    /// LDR (immediate, post-index)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--immediate---Load-Register--immediate-->
+    pub fn ldr_post(rt: u8, rn: u8, imm9: i16, num_bits: u8) -> Self {
+        Self { rt, rn, idx: Index::PostIndex, imm9, opc: Opc::LDR, size: num_bits.into() }
+    }
+
+    /// LDR (immediate, pre-index)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--immediate---Load-Register--immediate-->
+    pub fn ldr_pre(rt: u8, rn: u8, imm9: i16, num_bits: u8) -> Self {
+        Self { rt, rn, idx: Index::PreIndex, imm9, opc: Opc::LDR, size: num_bits.into() }
+    }
+
+    /// LDUR (load register, unscaled)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDUR--Load-Register--unscaled--?lang=en>
+    pub fn ldur(rt: u8, rn: u8, imm9: i16, num_bits: u8) -> Self {
+        Self { rt, rn, idx: Index::None, imm9, opc: Opc::LDR, size: num_bits.into() }
+    }
+
+    /// LDURH Load Register Halfword (unscaled)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDURH--Load-Register-Halfword--unscaled--?lang=en>
+    pub fn ldurh(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, idx: Index::None, imm9, opc: Opc::LDR, size: Size::Size16 }
+    }
+
+    /// LDURB (load register, byte, unscaled)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDURB--Load-Register-Byte--unscaled--?lang=en>
+    pub fn ldurb(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, idx: Index::None, imm9, opc: Opc::LDR, size: Size::Size8 }
+    }
+
+    /// LDURSW (load register, unscaled, signed)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDURSW--Load-Register-Signed-Word--unscaled--?lang=en>
+    pub fn ldursw(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, idx: Index::None, imm9, opc: Opc::LDURSW, size: Size::Size32 }
+    }
+
+    /// STR (immediate, post-index)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STR--immediate---Store-Register--immediate-->
+    pub fn str_post(rt: u8, rn: u8, imm9: i16, num_bits: u8) -> Self {
+        Self { rt, rn, idx: Index::PostIndex, imm9, opc: Opc::STR, size: num_bits.into() }
+    }
+
+    /// STR (immediate, pre-index)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STR--immediate---Store-Register--immediate-->
+    pub fn str_pre(rt: u8, rn: u8, imm9: i16, num_bits: u8) -> Self {
+        Self { rt, rn, idx: Index::PreIndex, imm9, opc: Opc::STR, size: num_bits.into() }
+    }
+
+    /// STUR (store register, unscaled)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STUR--Store-Register--unscaled--?lang=en>
+    pub fn stur(rt: u8, rn: u8, imm9: i16, num_bits: u8) -> Self {
+        Self { rt, rn, idx: Index::None, imm9, opc: Opc::STR, size: num_bits.into() }
+    }
+
+    /// STURH (store register, halfword, unscaled)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STURH--Store-Register-Halfword--unscaled--?lang=en>
+    pub fn sturh(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, idx: Index::None, imm9, opc: Opc::STR, size: Size::Size16 }
+    }
+
+    /// STURB (store register, byte, unscaled)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STURH--Store-Register-Halfword--unscaled--?lang=en>
+    pub fn sturb(rt: u8, rn: u8, imm9: i16) -> Self {
+        Self { rt, rn, idx: Index::None, imm9, opc: Opc::STR, size: Size::Size8 }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en>
+const FAMILY: u32 = 0b0100;
+
+impl From<LoadStore> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: LoadStore) -> Self {
+        0
+        | ((inst.size as u32) << 30)
+        | (0b11 << 28)
+        | (FAMILY << 25)
+        | ((inst.opc as u32) << 22)
+        | (truncate_imm::<_, 9>(inst.imm9) << 12)
+        | ((inst.idx as u32) << 10)
+        | ((inst.rn as u32) << 5)
+        | (inst.rt as u32)
+    }
+}
+
+impl From<LoadStore> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: LoadStore) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_ldr_post() {
+        let inst = LoadStore::ldr_post(0, 1, 16, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf8410420, result);
+    }
+
+    #[test]
+    fn test_ldr_pre() {
+        let inst = LoadStore::ldr_pre(0, 1, 16, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf8410c20, result);
+    }
+
+    #[test]
+    fn test_ldur() {
+        let inst = LoadStore::ldur(0, 1, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf8400020, result);
+    }
+
+    #[test]
+    fn test_ldurb() {
+        let inst = LoadStore::ldurb(0, 1, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0x38400020, result);
+    }
+
+    #[test]
+    fn test_ldurh() {
+        let inst = LoadStore::ldurh(0, 1, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0x78400020, result);
+    }
+
+    #[test]
+    fn test_ldur_with_imm() {
+        let inst = LoadStore::ldur(0, 1, 123, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf847b020, result);
+    }
+
+    #[test]
+    fn test_ldursw() {
+        let inst = LoadStore::ldursw(0, 1, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0xb8800020, result);
+    }
+
+    #[test]
+    fn test_ldursw_with_imm() {
+        let inst = LoadStore::ldursw(0, 1, 123);
+        let result: u32 = inst.into();
+        assert_eq!(0xb887b020, result);
+    }
+
+    #[test]
+    fn test_str_post() {
+        let inst = LoadStore::str_post(0, 1, -16, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf81f0420, result);
+    }
+
+    #[test]
+    fn test_str_pre() {
+        let inst = LoadStore::str_pre(0, 1, -16, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf81f0c20, result);
+    }
+
+    #[test]
+    fn test_stur() {
+        let inst = LoadStore::stur(0, 1, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf8000020, result);
+    }
+
+    #[test]
+    fn test_stur_negative_offset() {
+        let inst = LoadStore::stur(0, 1, -1, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf81ff020, result);
+    }
+
+    #[test]
+    fn test_stur_positive_offset() {
+        let inst = LoadStore::stur(0, 1, 255, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf80ff020, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/load_store_exclusive.rs b/zjit/src/asm/arm64/inst/load_store_exclusive.rs
new file mode 100644
index 0000000000..30cb663bdb
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/load_store_exclusive.rs
@@ -0,0 +1,109 @@
+/// The operation being performed for this instruction.
+enum Op {
+    Store = 0,
+    Load = 1
+}
+
+/// The size of the registers being operated on.
+enum Size {
+    Size32 = 0b10,
+    Size64 = 0b11
+}
+
+/// A convenience function so that we can convert the number of bits of an
+/// register operand directly into a Size enum variant.
+impl From<u8> for Size {
+    fn from(num_bits: u8) -> Self {
+        match num_bits {
+            64 => Size::Size64,
+            32 => Size::Size32,
+            _ => panic!("Invalid number of bits: {num_bits}"),
+        }
+    }
+}
+
+/// The struct that represents an A64 load or store exclusive instruction that
+/// can be encoded.
+///
+/// LDAXR/STLXR
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  1     0  0    1  0  0  0    0     0                     1  1  1  1    1  1                                   |
+/// | size.                          op    rs..............                       rn.............. rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct LoadStoreExclusive {
+    /// The number of the register to be loaded.
+    rt: u8,
+
+    /// The base register with which to form the address.
+    rn: u8,
+
+    /// The register to be used for the status result if it applies to this
+    /// operation. Otherwise it's the zero register.
+    rs: u8,
+
+    /// The operation being performed for this instruction.
+    op: Op,
+
+    /// The size of the registers being operated on.
+    size: Size
+}
+
+impl LoadStoreExclusive {
+    /// LDAXR
+    /// <https://developer.arm.com/documentation/ddi0602/2021-12/Base-Instructions/LDAXR--Load-Acquire-Exclusive-Register->
+    pub fn ldaxr(rt: u8, rn: u8, num_bits: u8) -> Self {
+        Self { rt, rn, rs: 31, op: Op::Load, size: num_bits.into() }
+    }
+
+    /// STLXR
+    /// <https://developer.arm.com/documentation/ddi0602/2021-12/Base-Instructions/STLXR--Store-Release-Exclusive-Register->
+    pub fn stlxr(rs: u8, rt: u8, rn: u8, num_bits: u8) -> Self {
+        Self { rt, rn, rs, op: Op::Store, size: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en>
+const FAMILY: u32 = 0b0100;
+
+impl From<LoadStoreExclusive> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: LoadStoreExclusive) -> Self {
+        0
+        | ((inst.size as u32) << 30)
+        | (FAMILY << 25)
+        | ((inst.op as u32) << 22)
+        | ((inst.rs as u32) << 16)
+        | (0b111111 << 10)
+        | ((inst.rn as u32) << 5)
+        | (inst.rt as u32)
+    }
+}
+
+impl From<LoadStoreExclusive> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: LoadStoreExclusive) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_ldaxr() {
+        let inst = LoadStoreExclusive::ldaxr(16, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xc85ffc10, result);
+    }
+
+    #[test]
+    fn test_stlxr() {
+        let inst = LoadStoreExclusive::stlxr(17, 16, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xc811fc10, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/logical_imm.rs b/zjit/src/asm/arm64/inst/logical_imm.rs
new file mode 100644
index 0000000000..d57ad5f5b7
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/logical_imm.rs
@@ -0,0 +1,154 @@
+use super::super::arg::{BitmaskImmediate, Sf};
+
+// Which operation to perform.
+enum Opc {
+    /// The AND operation.
+    And = 0b00,
+
+    /// The ORR operation.
+    Orr = 0b01,
+
+    /// The EOR operation.
+    Eor = 0b10,
+
+    /// The ANDS operation.
+    Ands = 0b11
+}
+
+/// The struct that represents an A64 bitwise immediate instruction that can be
+/// encoded.
+///
+/// AND/ORR/ANDS (immediate)
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |           1    0  0  1  0    0                                                                                |
+/// | sf opc..                       N  immr...............   imms............... rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct LogicalImm {
+    /// The register number of the destination register.
+    rd: u8,
+
+    /// The register number of the first operand register.
+    rn: u8,
+
+    /// The immediate value to test.
+    imm: BitmaskImmediate,
+
+    /// The opcode for this instruction.
+    opc: Opc,
+
+    /// Whether or not this instruction is operating on 64-bit operands.
+    sf: Sf
+}
+
+impl LogicalImm {
+    /// AND (bitmask immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en>
+    pub fn and(rd: u8, rn: u8, imm: BitmaskImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, opc: Opc::And, sf: num_bits.into() }
+    }
+
+    /// ANDS (bitmask immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ANDS--immediate---Bitwise-AND--immediate---setting-flags-?lang=en>
+    pub fn ands(rd: u8, rn: u8, imm: BitmaskImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, opc: Opc::Ands, sf: num_bits.into() }
+    }
+
+    /// EOR (bitmask immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/EOR--immediate---Bitwise-Exclusive-OR--immediate-->
+    pub fn eor(rd: u8, rn: u8, imm: BitmaskImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, opc: Opc::Eor, sf: num_bits.into() }
+    }
+
+    /// MOV (bitmask immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MOV--bitmask-immediate---Move--bitmask-immediate---an-alias-of-ORR--immediate--?lang=en>
+    pub fn mov(rd: u8, imm: BitmaskImmediate, num_bits: u8) -> Self {
+        Self { rd, rn: 0b11111, imm, opc: Opc::Orr, sf: num_bits.into() }
+    }
+
+    /// ORR (bitmask immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ORR--immediate---Bitwise-OR--immediate-->
+    pub fn orr(rd: u8, rn: u8, imm: BitmaskImmediate, num_bits: u8) -> Self {
+        Self { rd, rn, imm, opc: Opc::Orr, sf: num_bits.into() }
+    }
+
+    /// TST (bitmask immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/TST--immediate---Test-bits--immediate---an-alias-of-ANDS--immediate--?lang=en>
+    pub fn tst(rn: u8, imm: BitmaskImmediate, num_bits: u8) -> Self {
+        Self::ands(31, rn, imm, num_bits)
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Immediate?lang=en#log_imm>
+const FAMILY: u32 = 0b1001;
+
+impl From<LogicalImm> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: LogicalImm) -> Self {
+        let imm: u32 = inst.imm.encode();
+
+        0
+        | ((inst.sf as u32) << 31)
+        | ((inst.opc as u32) << 29)
+        | (FAMILY << 25)
+        | (imm << 10)
+        | ((inst.rn as u32) << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<LogicalImm> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: LogicalImm) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_and() {
+        let inst = LogicalImm::and(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x92400820, result);
+    }
+
+    #[test]
+    fn test_ands() {
+        let inst = LogicalImm::ands(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf2400820, result);
+    }
+
+    #[test]
+    fn test_eor() {
+        let inst = LogicalImm::eor(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd2400820, result);
+    }
+
+    #[test]
+    fn test_mov() {
+        let inst = LogicalImm::mov(0, 0x5555555555555555.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xb200f3e0, result);
+    }
+
+    #[test]
+    fn test_orr() {
+        let inst = LogicalImm::orr(0, 1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xb2400820, result);
+    }
+
+    #[test]
+    fn test_tst() {
+        let inst = LogicalImm::tst(1, 7.try_into().unwrap(), 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf240083f, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/logical_reg.rs b/zjit/src/asm/arm64/inst/logical_reg.rs
new file mode 100644
index 0000000000..18edff606f
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/logical_reg.rs
@@ -0,0 +1,207 @@
+use super::super::arg::{Sf, truncate_uimm};
+
+/// Whether or not this is a NOT instruction.
+enum N {
+    /// This is not a NOT instruction.
+    No = 0,
+
+    /// This is a NOT instruction.
+    Yes = 1
+}
+
+/// The type of shift to perform on the second operand register.
+enum Shift {
+    LSL = 0b00, // logical shift left (unsigned)
+    LSR = 0b01, // logical shift right (unsigned)
+    ASR = 0b10, // arithmetic shift right (signed)
+    ROR = 0b11  // rotate right (unsigned)
+}
+
+// Which operation to perform.
+enum Opc {
+    /// The AND operation.
+    And = 0b00,
+
+    /// The ORR operation.
+    Orr = 0b01,
+
+    /// The EOR operation.
+    Eor = 0b10,
+
+    /// The ANDS operation.
+    Ands = 0b11
+}
+
+/// The struct that represents an A64 logical register instruction that can be
+/// encoded.
+///
+/// AND/ORR/ANDS (shifted register)
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |           0    1  0  1  0                                                                                     |
+/// | sf opc..                    shift N  rm..............   imm6............... rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct LogicalReg {
+    /// The register number of the destination register.
+    rd: u8,
+
+    /// The register number of the first operand register.
+    rn: u8,
+
+    /// The amount to shift the second operand register.
+    imm6: u8,
+
+    /// The register number of the second operand register.
+    rm: u8,
+
+    /// Whether or not this is a NOT instruction.
+    n: N,
+
+    /// The type of shift to perform on the second operand register.
+    shift: Shift,
+
+    /// The opcode for this instruction.
+    opc: Opc,
+
+    /// Whether or not this instruction is operating on 64-bit operands.
+    sf: Sf
+}
+
+impl LogicalReg {
+    /// AND (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--shifted-register---Bitwise-AND--shifted-register--?lang=en>
+    pub fn and(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn, imm6: 0, rm, n: N::No, shift: Shift::LSL, opc: Opc::And, sf: num_bits.into() }
+    }
+
+    /// ANDS (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ANDS--shifted-register---Bitwise-AND--shifted-register---setting-flags-?lang=en>
+    pub fn ands(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn, imm6: 0, rm, n: N::No, shift: Shift::LSL, opc: Opc::Ands, sf: num_bits.into() }
+    }
+
+    /// EOR (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/EOR--shifted-register---Bitwise-Exclusive-OR--shifted-register-->
+    pub fn eor(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn, imm6: 0, rm, n: N::No, shift: Shift::LSL, opc: Opc::Eor, sf: num_bits.into() }
+    }
+
+    /// MOV (register)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MOV--register---Move--register---an-alias-of-ORR--shifted-register--?lang=en>
+    pub fn mov(rd: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn: 0b11111, imm6: 0, rm, n: N::No, shift: Shift::LSL, opc: Opc::Orr, sf: num_bits.into() }
+    }
+
+    /// MVN (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MVN--Bitwise-NOT--an-alias-of-ORN--shifted-register--?lang=en>
+    pub fn mvn(rd: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn: 0b11111, imm6: 0, rm, n: N::Yes, shift: Shift::LSL, opc: Opc::Orr, sf: num_bits.into() }
+    }
+
+    /// ORN (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ORN--shifted-register---Bitwise-OR-NOT--shifted-register-->
+    pub fn orn(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn, imm6: 0, rm, n: N::Yes, shift: Shift::LSL, opc: Opc::Orr, sf: num_bits.into() }
+    }
+
+    /// ORR (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ORR--shifted-register---Bitwise-OR--shifted-register-->
+    pub fn orr(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn, imm6: 0, rm, n: N::No, shift: Shift::LSL, opc: Opc::Orr, sf: num_bits.into() }
+    }
+
+    /// TST (shifted register)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/TST--shifted-register---Test--shifted-register---an-alias-of-ANDS--shifted-register--?lang=en>
+    pub fn tst(rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd: 31, rn, imm6: 0, rm, n: N::No, shift: Shift::LSL, opc: Opc::Ands, sf: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Register?lang=en>
+const FAMILY: u32 = 0b0101;
+
+impl From<LogicalReg> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: LogicalReg) -> Self {
+        0
+        | ((inst.sf as u32) << 31)
+        | ((inst.opc as u32) << 29)
+        | (FAMILY << 25)
+        | ((inst.shift as u32) << 22)
+        | ((inst.n as u32) << 21)
+        | ((inst.rm as u32) << 16)
+        | (truncate_uimm::<_, 6>(inst.imm6) << 10)
+        | ((inst.rn as u32) << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<LogicalReg> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: LogicalReg) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_and() {
+        let inst = LogicalReg::and(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x8a020020, result);
+    }
+
+    #[test]
+    fn test_ands() {
+        let inst = LogicalReg::ands(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xea020020, result);
+    }
+
+    #[test]
+    fn test_eor() {
+        let inst = LogicalReg::eor(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xca020020, result);
+    }
+
+    #[test]
+    fn test_mov() {
+        let inst = LogicalReg::mov(0, 1, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xaa0103e0, result);
+    }
+
+    #[test]
+    fn test_mvn() {
+        let inst = LogicalReg::mvn(0, 1, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xaa2103e0, result);
+    }
+
+    #[test]
+    fn test_orn() {
+        let inst = LogicalReg::orn(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xaa220020, result);
+    }
+
+    #[test]
+    fn test_orr() {
+        let inst = LogicalReg::orr(0, 1, 2, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xaa020020, result);
+    }
+
+    #[test]
+    fn test_tst() {
+        let inst = LogicalReg::tst(0, 1, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xea01001f, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/madd.rs b/zjit/src/asm/arm64/inst/madd.rs
new file mode 100644
index 0000000000..71f2ab230a
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/madd.rs
@@ -0,0 +1,73 @@
+use super::super::arg::Sf;
+
+/// The struct that represents an A64 multiply-add instruction that can be
+/// encoded.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |     0  0  1    1  0  1  1    0  0  0                     0                                                    |
+/// | sf                                   rm..............      ra.............. rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct MAdd {
+    /// The number of the general-purpose destination register.
+    rd: u8,
+
+    /// The number of the first general-purpose source register.
+    rn: u8,
+
+    /// The number of the third general-purpose source register.
+    ra: u8,
+
+    /// The number of the second general-purpose source register.
+    rm: u8,
+
+    /// The size of the registers of this instruction.
+    sf: Sf
+}
+
+impl MAdd {
+    /// MUL
+    /// <https://developer.arm.com/documentation/ddi0602/2023-06/Base-Instructions/MUL--Multiply--an-alias-of-MADD->
+    pub fn mul(rd: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
+        Self { rd, rn, ra: 0b11111, rm, sf: num_bits.into() }
+    }
+}
+
+impl From<MAdd> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: MAdd) -> Self {
+        0
+        | ((inst.sf as u32) << 31)
+        | (0b11011 << 24)
+        | ((inst.rm as u32) << 16)
+        | ((inst.ra as u32) << 10)
+        | ((inst.rn as u32) << 5)
+        | (inst.rd as u32)
+    }
+}
+
+impl From<MAdd> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: MAdd) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mul_32() {
+        let result: u32 = MAdd::mul(0, 1, 2, 32).into();
+        assert_eq!(0x1B027C20, result);
+    }
+
+    #[test]
+    fn test_mul_64() {
+        let result: u32 = MAdd::mul(0, 1, 2, 64).into();
+        assert_eq!(0x9B027C20, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/mod.rs b/zjit/src/asm/arm64/inst/mod.rs
new file mode 100644
index 0000000000..270c784f27
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/mod.rs
@@ -0,0 +1,56 @@
+// This module contains various A64 instructions and the logic necessary to
+// encode them into u32s.
+
+mod atomic;
+mod branch;
+mod branch_cond;
+mod breakpoint;
+mod call;
+mod conditional;
+mod data_imm;
+mod data_reg;
+mod halfword_imm;
+mod load_literal;
+mod load_register;
+mod load_store;
+mod load_store_exclusive;
+mod logical_imm;
+mod logical_reg;
+mod madd;
+mod smulh;
+mod mov;
+mod nop;
+mod pc_rel;
+mod reg_pair;
+mod sbfm;
+mod shift_imm;
+mod sys_reg;
+mod test_bit;
+mod udf;
+
+pub use atomic::Atomic;
+pub use branch::Branch;
+pub use branch_cond::BranchCond;
+pub use breakpoint::Breakpoint;
+pub use call::Call;
+pub use conditional::Conditional;
+pub use data_imm::DataImm;
+pub use data_reg::DataReg;
+pub use halfword_imm::HalfwordImm;
+pub use load_literal::LoadLiteral;
+pub use load_register::LoadRegister;
+pub use load_store::LoadStore;
+pub use load_store_exclusive::LoadStoreExclusive;
+pub use logical_imm::LogicalImm;
+pub use logical_reg::LogicalReg;
+pub use madd::MAdd;
+pub use smulh::SMulH;
+pub use mov::Mov;
+pub use nop::Nop;
+pub use pc_rel::PCRelative;
+pub use reg_pair::RegisterPair;
+pub use sbfm::SBFM;
+pub use shift_imm::ShiftImm;
+pub use sys_reg::SysReg;
+pub use test_bit::TestBit;
+pub use udf::Udf;
diff --git a/zjit/src/asm/arm64/inst/mov.rs b/zjit/src/asm/arm64/inst/mov.rs
new file mode 100644
index 0000000000..e9f9091713
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/mov.rs
@@ -0,0 +1,192 @@
+use super::super::arg::Sf;
+
+/// Which operation is being performed.
+enum Op {
+    /// A movn operation which inverts the immediate and zeroes out the other bits.
+    MOVN = 0b00,
+
+    /// A movz operation which zeroes out the other bits.
+    MOVZ = 0b10,
+
+    /// A movk operation which keeps the other bits in place.
+    MOVK = 0b11
+}
+
+/// How much to shift the immediate by.
+enum Hw {
+    LSL0 = 0b00,
+    LSL16 = 0b01,
+    LSL32 = 0b10,
+    LSL48 = 0b11
+}
+
+impl From<u8> for Hw {
+    fn from(shift: u8) -> Self {
+        match shift {
+            0 => Hw::LSL0,
+            16 => Hw::LSL16,
+            32 => Hw::LSL32,
+            48 => Hw::LSL48,
+            _ => panic!("Invalid value for shift: {shift}"),
+        }
+    }
+}
+
+/// The struct that represents a MOVK or MOVZ instruction.
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |           1    0  0  1  0    1                                                                                |
+/// | sf op...                       hw... imm16.................................................. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct Mov {
+    /// The register number of the destination register.
+    rd: u8,
+
+    /// The value to move into the register.
+    imm16: u16,
+
+    /// The shift of the value to move.
+    hw: Hw,
+
+    /// Which operation is being performed.
+    op: Op,
+
+    /// Whether or not this instruction is operating on 64-bit operands.
+    sf: Sf
+}
+
+impl Mov {
+    /// MOVK
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/MOVK--Move-wide-with-keep-?lang=en>
+    pub fn movk(rd: u8, imm16: u16, hw: u8, num_bits: u8) -> Self {
+        Self { rd, imm16, hw: hw.into(), op: Op::MOVK, sf: num_bits.into() }
+    }
+
+    /// MOVN
+    /// <https://developer.arm.com/documentation/ddi0602/2025-06/Base-Instructions/MOVN--Move-wide-with-NOT->
+    pub fn movn(rd: u8, imm16: u16, hw: u8, num_bits: u8) -> Self {
+        Self { rd, imm16, hw: hw.into(), op: Op::MOVN, sf: num_bits.into() }
+    }
+
+    /// MOVZ
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/MOVZ--Move-wide-with-zero-?lang=en>
+    pub fn movz(rd: u8, imm16: u16, hw: u8, num_bits: u8) -> Self {
+        Self { rd, imm16, hw: hw.into(), op: Op::MOVZ, sf: num_bits.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Immediate?lang=en>
+const FAMILY: u32 = 0b1000;
+
+impl From<Mov> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: Mov) -> Self {
+        0
+        | ((inst.sf as u32) << 31)
+        | ((inst.op as u32) << 29)
+        | (FAMILY << 25)
+        | (0b101 << 23)
+        | ((inst.hw as u32) << 21)
+        | ((inst.imm16 as u32) << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<Mov> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: Mov) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_movk_unshifted() {
+        let inst = Mov::movk(0, 123, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf2800f60, result);
+    }
+
+    #[test]
+    fn test_movn_unshifted() {
+        let inst = Mov::movn(0, 123, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x92800f60, result);
+    }
+
+    #[test]
+    fn test_movn_shifted_16() {
+        let inst = Mov::movn(0, 123, 16, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x92a00f60, result);
+    }
+
+    #[test]
+    fn test_movn_shifted_32() {
+        let inst = Mov::movn(0, 123, 32, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x92c00f60, result);
+    }
+
+    #[test]
+    fn test_movn_shifted_48() {
+        let inst = Mov::movn(0, 123, 48, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x92e00f60, result);
+    }
+
+    #[test]
+    fn test_movk_shifted_16() {
+        let inst = Mov::movk(0, 123, 16, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf2a00f60, result);
+    }
+
+    #[test]
+    fn test_movk_shifted_32() {
+        let inst = Mov::movk(0, 123, 32, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf2c00f60, result);
+    }
+
+    #[test]
+    fn test_movk_shifted_48() {
+        let inst = Mov::movk(0, 123, 48, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xf2e00f60, result);
+    }
+
+    #[test]
+    fn test_movz_unshifted() {
+        let inst = Mov::movz(0, 123, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd2800f60, result);
+    }
+
+    #[test]
+    fn test_movz_shifted_16() {
+        let inst = Mov::movz(0, 123, 16, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd2a00f60, result);
+    }
+
+    #[test]
+    fn test_movz_shifted_32() {
+        let inst = Mov::movz(0, 123, 32, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd2c00f60, result);
+    }
+
+    #[test]
+    fn test_movz_shifted_48() {
+        let inst = Mov::movz(0, 123, 48, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd2e00f60, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/nop.rs b/zjit/src/asm/arm64/inst/nop.rs
new file mode 100644
index 0000000000..081d8558f5
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/nop.rs
@@ -0,0 +1,44 @@
+/// The struct that represents an A64 nop instruction that can be encoded.
+///
+/// NOP
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  1  1  0  1    0  1  0  1    0  0  0  0    0  0  1  1    0  0  1  0    0  0  0  0    0  0  0  1    1  1  1  1 |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct Nop;
+
+impl Nop {
+    /// NOP
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/NOP--No-Operation->
+    pub fn nop() -> Self {
+        Self {}
+    }
+}
+
+impl From<Nop> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(_inst: Nop) -> Self {
+        0b11010101000000110010000000011111
+    }
+}
+
+impl From<Nop> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: Nop) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_nop() {
+        let inst = Nop::nop();
+        let result: u32 = inst.into();
+        assert_eq!(0xd503201f, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/pc_rel.rs b/zjit/src/asm/arm64/inst/pc_rel.rs
new file mode 100644
index 0000000000..2ea586a778
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/pc_rel.rs
@@ -0,0 +1,107 @@
+/// Which operation to perform for the PC-relative instruction.
+enum Op {
+    /// Form a PC-relative address.
+    ADR = 0,
+
+    /// Form a PC-relative address to a 4KB page.
+    ADRP = 1
+}
+
+/// The struct that represents an A64 PC-relative address instruction that can
+/// be encoded.
+///
+/// ADR
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |           1    0  0  0  0                                                                                     |
+/// | op immlo                    immhi........................................................... rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct PCRelative {
+    /// The number for the general-purpose register to load the address into.
+    rd: u8,
+
+    /// The number of bytes to add to the PC to form the address.
+    imm: i32,
+
+    /// Which operation to perform for this instruction.
+    op: Op
+}
+
+impl PCRelative {
+    /// ADR
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/ADR--Form-PC-relative-address->
+    pub fn adr(rd: u8, imm: i32) -> Self {
+        Self { rd, imm, op: Op::ADR }
+    }
+
+    /// ADRP
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/ADRP--Form-PC-relative-address-to-4KB-page->
+    pub fn adrp(rd: u8, imm: i32) -> Self {
+        Self { rd, imm: imm >> 12, op: Op::ADRP }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Immediate?lang=en>
+const FAMILY: u32 = 0b1000;
+
+impl From<PCRelative> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: PCRelative) -> Self {
+        let immlo = (inst.imm & 0b11) as u32;
+        let mut immhi = ((inst.imm >> 2) & ((1 << 18) - 1)) as u32;
+
+        // Toggle the sign bit if necessary.
+        if inst.imm < 0 {
+            immhi |= 1 << 18;
+        }
+
+        0
+        | ((inst.op as u32) << 31)
+        | (immlo << 29)
+        | (FAMILY << 25)
+        | (immhi << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<PCRelative> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: PCRelative) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_adr_positive() {
+        let inst = PCRelative::adr(0, 5);
+        let result: u32 = inst.into();
+        assert_eq!(0x30000020, result);
+    }
+
+    #[test]
+    fn test_adr_negative() {
+        let inst = PCRelative::adr(0, -5);
+        let result: u32 = inst.into();
+        assert_eq!(0x70ffffc0, result);
+    }
+
+    #[test]
+    fn test_adrp_positive() {
+        let inst = PCRelative::adrp(0, 0x4000);
+        let result: u32 = inst.into();
+        assert_eq!(0x90000020, result);
+    }
+
+    #[test]
+    fn test_adrp_negative() {
+        let inst = PCRelative::adrp(0, -0x4000);
+        let result: u32 = inst.into();
+        assert_eq!(0x90ffffe0, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/reg_pair.rs b/zjit/src/asm/arm64/inst/reg_pair.rs
new file mode 100644
index 0000000000..39a44c2416
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/reg_pair.rs
@@ -0,0 +1,212 @@
+use super::super::arg::truncate_imm;
+
+/// The operation to perform for this instruction.
+enum Opc {
+    /// When the registers are 32-bits wide.
+    Opc32 = 0b00,
+
+    /// When the registers are 64-bits wide.
+    Opc64 = 0b10
+}
+
+/// The kind of indexing to perform for this instruction.
+enum Index {
+    StorePostIndex = 0b010,
+    LoadPostIndex = 0b011,
+    StoreSignedOffset = 0b100,
+    LoadSignedOffset = 0b101,
+    StorePreIndex = 0b110,
+    LoadPreIndex = 0b111
+}
+
+/// A convenience function so that we can convert the number of bits of a
+/// register operand directly into an Opc variant.
+impl From<u8> for Opc {
+    fn from(num_bits: u8) -> Self {
+        match num_bits {
+            64 => Opc::Opc64,
+            32 => Opc::Opc32,
+            _ => panic!("Invalid number of bits: {num_bits}"),
+        }
+    }
+}
+
+/// The struct that represents an A64 register pair instruction that can be
+/// encoded.
+///
+/// STP/LDP
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |     0  1  0    1  0  0                                                                                        |
+/// | opc                    index..... imm7.................... rt2............. rn.............. rt1............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct RegisterPair {
+    /// The number of the first register to be transferred.
+    rt1: u8,
+
+    /// The number of the base register.
+    rn: u8,
+
+    /// The number of the second register to be transferred.
+    rt2: u8,
+
+    /// The signed immediate byte offset, a multiple of 8.
+    imm7: i16,
+
+    /// The kind of indexing to use for this instruction.
+    index: Index,
+
+    /// The operation to be performed (in terms of size).
+    opc: Opc
+}
+
+impl RegisterPair {
+    /// Create a register pair instruction with a given indexing mode.
+    fn new(rt1: u8, rt2: u8, rn: u8, disp: i16, index: Index, num_bits: u8) -> Self {
+        Self { rt1, rn, rt2, imm7: disp / 8, index, opc: num_bits.into() }
+    }
+
+    /// LDP (signed offset)
+    /// `LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]`
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDP--Load-Pair-of-Registers-?lang=en>
+    pub fn ldp(rt1: u8, rt2: u8, rn: u8, disp: i16, num_bits: u8) -> Self {
+        Self::new(rt1, rt2, rn, disp, Index::LoadSignedOffset, num_bits)
+    }
+
+    /// LDP (pre-index)
+    /// `LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!`
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDP--Load-Pair-of-Registers-?lang=en>
+    pub fn ldp_pre(rt1: u8, rt2: u8, rn: u8, disp: i16, num_bits: u8) -> Self {
+        Self::new(rt1, rt2, rn, disp, Index::LoadPreIndex, num_bits)
+    }
+
+    /// LDP (post-index)
+    /// `LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>`
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDP--Load-Pair-of-Registers-?lang=en>
+    pub fn ldp_post(rt1: u8, rt2: u8, rn: u8, disp: i16, num_bits: u8) -> Self {
+        Self::new(rt1, rt2, rn, disp, Index::LoadPostIndex, num_bits)
+    }
+
+    /// STP (signed offset)
+    /// `STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]`
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STP--Store-Pair-of-Registers-?lang=en>
+    pub fn stp(rt1: u8, rt2: u8, rn: u8, disp: i16, num_bits: u8) -> Self {
+        Self::new(rt1, rt2, rn, disp, Index::StoreSignedOffset, num_bits)
+    }
+
+    /// STP (pre-index)
+    /// `STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!`
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STP--Store-Pair-of-Registers-?lang=en>
+    pub fn stp_pre(rt1: u8, rt2: u8, rn: u8, disp: i16, num_bits: u8) -> Self {
+        Self::new(rt1, rt2, rn, disp, Index::StorePreIndex, num_bits)
+    }
+
+    /// STP (post-index)
+    /// `STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>`
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STP--Store-Pair-of-Registers-?lang=en>
+    pub fn stp_post(rt1: u8, rt2: u8, rn: u8, disp: i16, num_bits: u8) -> Self {
+        Self::new(rt1, rt2, rn, disp, Index::StorePostIndex, num_bits)
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en>
+const FAMILY: u32 = 0b0100;
+
+impl From<RegisterPair> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: RegisterPair) -> Self {
+        0
+        | ((inst.opc as u32) << 30)
+        | (1 << 29)
+        | (FAMILY << 25)
+        | ((inst.index as u32) << 22)
+        | (truncate_imm::<_, 7>(inst.imm7) << 15)
+        | ((inst.rt2 as u32) << 10)
+        | ((inst.rn as u32) << 5)
+        | (inst.rt1 as u32)
+    }
+}
+
+impl From<RegisterPair> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: RegisterPair) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_ldp() {
+        let inst = RegisterPair::ldp(0, 1, 2, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa9400440, result);
+    }
+
+    #[test]
+    fn test_ldp_maximum_displacement() {
+        let inst = RegisterPair::ldp(0, 1, 2, 504, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa95f8440, result);
+    }
+
+    #[test]
+    fn test_ldp_minimum_displacement() {
+        let inst = RegisterPair::ldp(0, 1, 2, -512, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa9600440, result);
+    }
+
+    #[test]
+    fn test_ldp_pre() {
+        let inst = RegisterPair::ldp_pre(0, 1, 2, 256, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa9d00440, result);
+    }
+
+    #[test]
+    fn test_ldp_post() {
+        let inst = RegisterPair::ldp_post(0, 1, 2, 256, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa8d00440, result);
+    }
+
+    #[test]
+    fn test_stp() {
+        let inst = RegisterPair::stp(0, 1, 2, 0, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa9000440, result);
+    }
+
+    #[test]
+    fn test_stp_maximum_displacement() {
+        let inst = RegisterPair::stp(0, 1, 2, 504, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa91f8440, result);
+    }
+
+    #[test]
+    fn test_stp_minimum_displacement() {
+        let inst = RegisterPair::stp(0, 1, 2, -512, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa9200440, result);
+    }
+
+    #[test]
+    fn test_stp_pre() {
+        let inst = RegisterPair::stp_pre(0, 1, 2, 256, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa9900440, result);
+    }
+
+    #[test]
+    fn test_stp_post() {
+        let inst = RegisterPair::stp_post(0, 1, 2, 256, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xa8900440, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/sbfm.rs b/zjit/src/asm/arm64/inst/sbfm.rs
new file mode 100644
index 0000000000..12944ba722
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/sbfm.rs
@@ -0,0 +1,103 @@
+use super::super::arg::{Sf, truncate_uimm};
+
+/// The struct that represents an A64 signed bitfield move instruction that can
+/// be encoded.
+///
+/// SBFM
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |     0  0  1    0  0  1  1    0                                                                                |
+/// | sf                             N  immr...............   imms............... rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct SBFM {
+    /// The number for the general-purpose register to load the value into.
+    rd: u8,
+
+    /// The number for the general-purpose register to copy from.
+    rn: u8,
+
+    /// The leftmost bit number to be moved from the source.
+    imms: u8,
+
+    // The right rotate amount.
+    immr: u8,
+
+    /// Whether or not this is a 64-bit operation.
+    n: bool,
+
+    /// The size of this operation.
+    sf: Sf
+}
+
+impl SBFM {
+    /// ASR
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ASR--immediate---Arithmetic-Shift-Right--immediate---an-alias-of-SBFM-?lang=en>
+    pub fn asr(rd: u8, rn: u8, shift: u8, num_bits: u8) -> Self {
+        let (imms, n) = if num_bits == 64 {
+            (0b111111, true)
+        } else {
+            (0b011111, false)
+        };
+
+        Self { rd, rn, immr: shift, imms, n, sf: num_bits.into() }
+    }
+
+    /// SXTW
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SXTW--Sign-Extend-Word--an-alias-of-SBFM-?lang=en>
+    pub fn sxtw(rd: u8, rn: u8) -> Self {
+        Self { rd, rn, immr: 0, imms: 31, n: true, sf: Sf::Sf64 }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Immediate?lang=en#bitfield>
+const FAMILY: u32 = 0b1001;
+
+impl From<SBFM> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: SBFM) -> Self {
+        0
+        | ((inst.sf as u32) << 31)
+        | (FAMILY << 25)
+        | (1 << 24)
+        | ((inst.n as u32) << 22)
+        | (truncate_uimm::<_, 6>(inst.immr) << 16)
+        | (truncate_uimm::<_, 6>(inst.imms) << 10)
+        | ((inst.rn as u32) << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<SBFM> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: SBFM) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_asr_32_bits() {
+        let inst = SBFM::asr(0, 1, 2, 32);
+        let result: u32 = inst.into();
+        assert_eq!(0x13027c20, result);
+    }
+
+    #[test]
+    fn test_asr_64_bits() {
+        let inst = SBFM::asr(10, 11, 5, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0x9345fd6a, result);
+    }
+
+    #[test]
+    fn test_sxtw() {
+        let inst = SBFM::sxtw(0, 1);
+        let result: u32 = inst.into();
+        assert_eq!(0x93407c20, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/shift_imm.rs b/zjit/src/asm/arm64/inst/shift_imm.rs
new file mode 100644
index 0000000000..9dac9a1408
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/shift_imm.rs
@@ -0,0 +1,147 @@
+use super::super::arg::Sf;
+
+/// The operation to perform for this instruction.
+enum Opc {
+    /// Logical left shift
+    LSL,
+
+    /// Logical shift right
+    LSR
+}
+
+/// The struct that represents an A64 unsigned bitfield move instruction that
+/// can be encoded.
+///
+/// LSL (immediate)
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |     1  0  1    0  0  1  1    0                                                                                |
+/// | sf                             N  immr...............   imms............... rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct ShiftImm {
+    /// The register number of the destination register.
+    rd: u8,
+
+    /// The register number of the first operand register.
+    rn: u8,
+
+    /// The immediate value to shift by.
+    shift: u8,
+
+    /// The opcode for this instruction.
+    opc: Opc,
+
+    /// Whether or not this instruction is operating on 64-bit operands.
+    sf: Sf
+}
+
+impl ShiftImm {
+    /// LSL (immediate)
+    /// <https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LSL--immediate---Logical-Shift-Left--immediate---an-alias-of-UBFM-?lang=en>
+    pub fn lsl(rd: u8, rn: u8, shift: u8, num_bits: u8) -> Self {
+        ShiftImm { rd, rn, shift, opc: Opc::LSL, sf: num_bits.into() }
+    }
+
+    /// LSR (immediate)
+    /// <https://developer.arm.com/documentation/ddi0602/2021-12/Base-Instructions/LSR--immediate---Logical-Shift-Right--immediate---an-alias-of-UBFM-?lang=en>
+    pub fn lsr(rd: u8, rn: u8, shift: u8, num_bits: u8) -> Self {
+        ShiftImm { rd, rn, shift, opc: Opc::LSR, sf: num_bits.into() }
+    }
+
+    /// Returns a triplet of (n, immr, imms) encoded in u32s for this
+    /// instruction. This mirrors how they will be encoded in the actual bits.
+    fn bitmask(&self) -> (u32, u32, u32) {
+        match self.opc {
+            // The key insight is a little buried in the docs, but effectively:
+            // LSL <Wd>, <Wn>, #<shift> == UBFM <Wd>, <Wn>, #(-<shift> MOD 32), #(31-<shift>)
+            // LSL <Xd>, <Xn>, #<shift> == UBFM <Xd>, <Xn>, #(-<shift> MOD 64), #(63-<shift>)
+            Opc::LSL => {
+                let shift = -(self.shift as i16);
+
+                match self.sf {
+                    Sf::Sf32 => (
+                        0,
+                        (shift.rem_euclid(32) & 0x3f) as u32,
+                        ((31 - self.shift) & 0x3f) as u32
+                    ),
+                    Sf::Sf64 => (
+                        1,
+                        (shift.rem_euclid(64) & 0x3f) as u32,
+                        ((63 - self.shift) & 0x3f) as u32
+                    )
+                }
+            },
+            // Similar to LSL:
+            // LSR <Wd>, <Wn>, #<shift> == UBFM <Wd>, <Wn>, #<shift>, #31
+            // LSR <Xd>, <Xn>, #<shift> == UBFM <Xd>, <Xn>, #<shift>, #63
+            Opc::LSR => {
+                match self.sf {
+                    Sf::Sf32 => (0, (self.shift & 0x3f) as u32, 31),
+                    Sf::Sf64 => (1, (self.shift & 0x3f) as u32, 63)
+                }
+            }
+        }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Immediate?lang=en#bitfield>
+const FAMILY: u32 = 0b10011;
+
+impl From<ShiftImm> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: ShiftImm) -> Self {
+        let (n, immr, imms) = inst.bitmask();
+
+        0
+        | ((inst.sf as u32) << 31)
+        | (1 << 30)
+        | (FAMILY << 24)
+        | (n << 22)
+        | (immr << 16)
+        | (imms << 10)
+        | ((inst.rn as u32) << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<ShiftImm> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: ShiftImm) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_lsl_32() {
+        let inst = ShiftImm::lsl(0, 1, 7, 32);
+        let result: u32 = inst.into();
+        assert_eq!(0x53196020, result);
+    }
+
+    #[test]
+    fn test_lsl_64() {
+        let inst = ShiftImm::lsl(0, 1, 7, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd379e020, result);
+    }
+
+    #[test]
+    fn test_lsr_32() {
+        let inst = ShiftImm::lsr(0, 1, 7, 32);
+        let result: u32 = inst.into();
+        assert_eq!(0x53077c20, result);
+    }
+
+    #[test]
+    fn test_lsr_64() {
+        let inst = ShiftImm::lsr(0, 1, 7, 64);
+        let result: u32 = inst.into();
+        assert_eq!(0xd347fc20, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/smulh.rs b/zjit/src/asm/arm64/inst/smulh.rs
new file mode 100644
index 0000000000..f355cb6531
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/smulh.rs
@@ -0,0 +1,60 @@
+/// The struct that represents an A64 signed multiply high instruction
+///
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  1  0  0  1    1  0  1  1    0  1  0                     0                                                    |
+/// |                                      rm..............      ra.............. rn.............. rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct SMulH {
+    /// The number of the general-purpose destination register.
+    rd: u8,
+
+    /// The number of the first general-purpose source register.
+    rn: u8,
+
+    /// The number of the third general-purpose source register.
+    ra: u8,
+
+    /// The number of the second general-purpose source register.
+    rm: u8,
+}
+
+impl SMulH {
+    /// SMULH
+    /// <https://developer.arm.com/documentation/ddi0602/2023-06/Base-Instructions/SMULH--Signed-Multiply-High->
+    pub fn smulh(rd: u8, rn: u8, rm: u8) -> Self {
+        Self { rd, rn, ra: 0b11111, rm }
+    }
+}
+
+impl From<SMulH> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: SMulH) -> Self {
+        0
+        | (0b10011011010 << 21)
+        | ((inst.rm as u32) << 16)
+        | ((inst.ra as u32) << 10)
+        | ((inst.rn as u32) << 5)
+        | (inst.rd as u32)
+    }
+}
+
+impl From<SMulH> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: SMulH) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_smulh() {
+        let result: u32 = SMulH::smulh(0, 1, 2).into();
+        assert_eq!(0x9b427c20, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/sys_reg.rs b/zjit/src/asm/arm64/inst/sys_reg.rs
new file mode 100644
index 0000000000..7191dfbfd9
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/sys_reg.rs
@@ -0,0 +1,86 @@
+use super::super::arg::SystemRegister;
+
+/// Which operation to perform (loading or storing the system register value).
+enum L {
+    /// Store the value of a general-purpose register in a system register.
+    MSR = 0,
+
+    /// Store the value of a system register in a general-purpose register.
+    MRS = 1
+}
+
+/// The struct that represents an A64 system register instruction that can be
+/// encoded.
+///
+/// MSR/MRS (register)
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |  1  1  0  1    0  1  0  1    0  0     1                                                                       |
+/// |                                   L       o0 op1.....   CRn........   CRm........   op2..... rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct SysReg {
+    /// The register to load the system register value into.
+    rt: u8,
+
+    /// Which system register to load or store.
+    systemreg: SystemRegister,
+
+    /// Which operation to perform (loading or storing the system register value).
+    l: L
+}
+
+impl SysReg {
+    /// MRS (register)
+    /// <https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/MRS--Move-System-Register-?lang=en>
+    pub fn mrs(rt: u8, systemreg: SystemRegister) -> Self {
+        SysReg { rt, systemreg, l: L::MRS }
+    }
+
+    /// MSR (register)
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/MSR--register---Move-general-purpose-register-to-System-Register-?lang=en>
+    pub fn msr(systemreg: SystemRegister, rt: u8) -> Self {
+        SysReg { rt, systemreg, l: L::MSR }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions?lang=en#systemmove>
+const FAMILY: u32 = 0b110101010001;
+
+impl From<SysReg> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: SysReg) -> Self {
+        0
+        | (FAMILY << 20)
+        | ((inst.l as u32) << 21)
+        | ((inst.systemreg as u32) << 5)
+        | inst.rt as u32
+    }
+}
+
+impl From<SysReg> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: SysReg) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mrs() {
+        let inst = SysReg::mrs(0, SystemRegister::NZCV);
+        let result: u32 = inst.into();
+        assert_eq!(0xd53b4200, result);
+    }
+
+    #[test]
+    fn test_msr() {
+        let inst = SysReg::msr(SystemRegister::NZCV, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0xd51b4200, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/test_bit.rs b/zjit/src/asm/arm64/inst/test_bit.rs
new file mode 100644
index 0000000000..45f0c2317e
--- /dev/null
+++ b/zjit/src/asm/arm64/inst/test_bit.rs
@@ -0,0 +1,133 @@
+use super::super::arg::truncate_imm;
+
+/// The upper bit of the bit number to test.
+#[derive(Debug)]
+enum B5 {
+    /// When the bit number is below 32.
+    B532 = 0,
+
+    /// When the bit number is equal to or above 32.
+    B564 = 1
+}
+
+/// A convenience function so that we can convert the bit number directly into a
+/// B5 variant.
+impl From<u8> for B5 {
+    fn from(bit_num: u8) -> Self {
+        match bit_num {
+            0..=31 => B5::B532,
+            32..=63 => B5::B564,
+            _ => panic!("Invalid bit number: {bit_num}"),
+        }
+    }
+}
+
+/// The operation to perform for this instruction.
+enum Op {
+    /// The test bit zero operation.
+    TBZ = 0,
+
+    /// The test bit not zero operation.
+    TBNZ = 1
+}
+
+/// The struct that represents an A64 test bit instruction that can be encoded.
+///
+/// TBNZ/TBZ
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |     0  1  1    0  1  1                                                                                        |
+/// | b5                     op   b40............. imm14.......................................... rt.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct TestBit {
+    /// The number of the register to test.
+    rt: u8,
+
+    /// The PC-relative offset to the target instruction in term of number of
+    /// instructions.
+    imm14: i16,
+
+    /// The lower 5 bits of the bit number to be tested.
+    b40: u8,
+
+    /// The operation to perform for this instruction.
+    op: Op,
+
+    /// The upper bit of the bit number to test.
+    b5: B5
+}
+
+impl TestBit {
+    /// TBNZ
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/TBNZ--Test-bit-and-Branch-if-Nonzero-?lang=en>
+    pub fn tbnz(rt: u8, bit_num: u8, offset: i16) -> Self {
+        Self { rt, imm14: offset, b40: bit_num & 0b11111, op: Op::TBNZ, b5: bit_num.into() }
+    }
+
+    /// TBZ
+    /// <https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/TBZ--Test-bit-and-Branch-if-Zero-?lang=en>
+    pub fn tbz(rt: u8, bit_num: u8, offset: i16) -> Self {
+        Self { rt, imm14: offset, b40: bit_num & 0b11111, op: Op::TBZ, b5: bit_num.into() }
+    }
+}
+
+/// <https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions?lang=en>
+const FAMILY: u32 = 0b11011;
+
+impl From<TestBit> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: TestBit) -> Self {
+        let b40 = (inst.b40 & 0b11111) as u32;
+        let imm14 = truncate_imm::<_, 14>(inst.imm14);
+
+        0
+        | ((inst.b5 as u32) << 31)
+        | (FAMILY << 25)
+        | ((inst.op as u32) << 24)
+        | (b40 << 19)
+        | (imm14 << 5)
+        | inst.rt as u32
+    }
+}
+
+impl From<TestBit> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: TestBit) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_tbnz() {
+        let inst = TestBit::tbnz(0, 0, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0x37000000, result);
+    }
+
+    #[test]
+    fn test_tbnz_negative() {
+        let inst = TestBit::tbnz(0, 0, -1);
+        let result: u32 = inst.into();
+        assert_eq!(0x3707ffe0, result);
+    }
+
+    #[test]
+    fn test_tbz() {
+        let inst = TestBit::tbz(0, 0, 0);
+        let result: u32 = inst.into();
+        assert_eq!(0x36000000, result);
+    }
+
+    #[test]
+    fn test_tbz_negative() {
+        let inst = TestBit::tbz(0, 0, -1);
+        let result: u32 = inst.into();
+        assert_eq!(0x3607ffe0, result);
+    }
+}
diff --git a/zjit/src/asm/arm64/inst/udf.rs b/zjit/src/asm/arm64/inst/udf.rs
new file mode 100644