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authorKevin Newton <kddnewton@gmail.com>2022-08-09 10:27:21 -0400
committerTakashi Kokubun <takashikkbn@gmail.com>2022-08-29 08:47:08 -0700
commitb8846dd2f8042fc13a0f5ae17e2e2a6f400074dd (patch)
treeccbba644d78f8d67e96495d810b8d2dd450b6538 /yjit/src/asm/arm64/inst/load_literal.rs
parent85d6d76e41b0c2cec64e3726d8218467954f5ee6 (diff)
Load mem displacement when necessary on AArch64 (https://github.com/Shopify/ruby/pull/382)
* LDR instruction for AArch64 * Split loads in arm64_split when memory address displacements do not fit
Diffstat (limited to 'yjit/src/asm/arm64/inst/load_literal.rs')
-rw-r--r--yjit/src/asm/arm64/inst/load_literal.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/yjit/src/asm/arm64/inst/load_literal.rs b/yjit/src/asm/arm64/inst/load_literal.rs
index a49130c3eb..d2a5d57eea 100644
--- a/yjit/src/asm/arm64/inst/load_literal.rs
+++ b/yjit/src/asm/arm64/inst/load_literal.rs
@@ -39,7 +39,7 @@ pub struct LoadLiteral {
impl LoadLiteral {
/// LDR (load literal)
/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--literal---Load-Register--literal--?lang=en
- pub fn ldr(rt: u8, imm19: i32, num_bits: u8) -> Self {
+ pub fn ldr_literal(rt: u8, imm19: i32, num_bits: u8) -> Self {
Self { rt, imm19, opc: num_bits.into() }
}
}
@@ -75,14 +75,14 @@ mod tests {
#[test]
fn test_ldr_positive() {
- let inst = LoadLiteral::ldr(0, 5, 64);
+ let inst = LoadLiteral::ldr_literal(0, 5, 64);
let result: u32 = inst.into();
assert_eq!(0x580000a0, result);
}
#[test]
fn test_ldr_negative() {
- let inst = LoadLiteral::ldr(0, -5, 64);
+ let inst = LoadLiteral::ldr_literal(0, -5, 64);
let result: u32 = inst.into();
assert_eq!(0x58ffff60, result);
}