ZJIT: A64: Fix bad operand swapping in `asm.sub(imm, reg)`

Previously, my buggy optimization would turn `asm.sub(imm, reg)`
into `subs out, reg, imm` since it runs through the addition path which
relies on the commutative property. Don't do that because subtraction
does not commute. Good thing no one seems to use this form.

Also, delete the 2 regs match arm for Add because it's already covered
by the fallback arm -- both split_load_operand() and
split_shifted_immediate() are no-op when the input is a register.

Fixes: 1317377fa74 ("ZJIT: A64: Have add/sub to SP be
single-instruction")

0 files changed, 0 insertions, 0 deletions