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* ADR and ADRP for AArch64
* Implement Op::Jbe on X86
* Lera instruction
* Op::BakeString
* LeaPC -> LeaLabel
* Port print_str to the new backend
* Port print_value to the new backend
* Port print_ptr to the new backend
* Write null-terminators in Op::BakeString
* Fix up rebase issues on print-str port
* Add back in panic for X86 backend for unsupported instructions being lowered
* Fix target architecture
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(https://github.com/Shopify/ruby/pull/319)
* Exclude X0 (C_RET_REG) from allocatable registers on arm
* Add another small test snippett
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Instructions for pushing all caller-save registers and the flags so that
we can implement dump_insns.
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(https://github.com/Shopify/ruby/pull/316)
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* Fix compile errors on arm on the CI
* Fix typo
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Previously we were using a `Box<dyn FnOnce>` to support patching the
code when jumping to labels. We needed to do this because some of the
closures that were being used to patch needed to capture local variables
(on both X86 and ARM it was the type of condition for the conditional
jumps).
To get around that, we can instead use const generics since the
condition codes are always known at compile-time. This means that the
closures go from polymorphic to monomorphic, which means they can be
represented as an `fn` instead of a `Box<dyn FnOnce>`, which means they
can fall back to a plain function pointer. This simplifies the storage
of the `LabelRef` structs and should hopefully be a better default
going forward.
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* Jumps for A64 should be in # of instructions
* More splitting for Arm64
https://github.com/Shopify/ruby/pull/309
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* More Arm64 lowering/backend work
* We now have encoding support for the LDR instruction for loading a PC-relative memory location
* You can now call add/adds/sub/subs with signed immediates, which switches appropriately based on sign
* We can now load immediates into registers appropriately, attempting to keep the minimal number of instructions:
* If it fits into 16 bytes, we use just a single movz.
* Else if it can be encoded into a bitmask immediate, we use a single mov.
* Otherwise we use a movz, a movk, and then optionally another one or two movks.
* Fixed a bunch of code to do with the Op::Load opcode.
* We now handle GC-offsets properly for Op::Load by skipping around them with a jump instruction. (This will be made better by constant pools in the future.)
* Op::Lea is doing what it's supposed to do now.
* Fixed a bug in the backend tests to do with not using the result of an Op::Add.
* Fix the remaining tests for Arm64
* Move split loads logic into each backend
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* Get initial wiring up
* Split IncrCounter instruction
* Breakpoints in Arm64
* Support for ORR
* MOV instruction encodings
* Implement JmpOpnd and CRet
* Add ORN
* Add MVN
* PUSH, POP, CCALL for Arm64
* Some formatting and implement Op::Not for Arm64
* Consistent constants when working with the Arm64 SP
* Allow OR-ing values into the memory buffer
* Test lowering Arm64 ADD
* Emit unconditional jumps consistently in Arm64
* Begin emitting conditional jumps for A64
* Back out some labelref changes
* Remove label API that no longer exists
* Use a trait for the label encoders
* Encode nop
* Add in nops so jumps are the same width no matter what on Arm64
* Op::Jbe for CodePtr
* Pass src_addr and dst_addr instead of calculated offset to label refs
* Even more jump work for Arm64
* Fix up jumps to use consistent assertions
* Handle splitting Add, Sub, and Not insns for Arm64
* More Arm64 splits and various fixes
* PR feedback for Arm64 support
* Split up jumps and conditional jump logic
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* LSL and LSR
* B.cond
* Move A64 files around to make more sense
* offset -> byte_offset for bcond
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The output from `dbg!` was too verbose. For `test_jo` the output went
from 37 lines to 5 lines. The added index helps parsing InsnOut
indicies.
Samples:
```
test backend::tests::test_jo ... [src/backend/ir.rs:589] &self = Assembler
000 Load(Mem64[Reg(3) + 8]) -> Out64(0)
001 Sub(Out64(0), 1_i64) -> Out64(1)
002 Load(Out64(1)) -> Out64(2)
003 Add(Out64(2), Mem64[Reg(3)]) -> Out64(3)
004 Jo() target=CodePtr(CodePtr(0x5)) -> Out64(4)
005 Mov(Mem64[Reg(3)], Out64(3)) -> Out64(5)
test backend::tests::test_reuse_reg ... [src/backend/ir.rs:589] &self = Assembler
000 Load(Mem64[Reg(3)]) -> Out64(0)
001 Add(Out64(0), 1_u64) -> Out64(1)
002 Load(Mem64[Reg(3) + 8]) -> Out64(2)
003 Add(Out64(2), 1_u64) -> Out64(3)
004 Add(Out64(1), 1_u64) -> Out64(4)
005 Add(Out64(1), Out64(4)) -> Out64(5)
006 Store(Mem64[Reg(3)], Out64(4)) -> Out64(6)
007 Store(Mem64[Reg(3) + 8], Out64(5)) -> Out64(7)
```
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* Add TST instruction and AND/ANDS entrypoints for immediates
* TST/AND/ANDS for registers
* CMP instruction
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