| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-08-29 | Port over get_branch_target() | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add jo insn and test for jo | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Port guard_two_fixnums | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Make sure allocated reg size in bits matches insn out size | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add Opnd.rm_num_bits() method | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Fix small bug in x86_split | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Get rid of temporary context methods | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add bitwise and to x86 backend | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add stores to one of the tests | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Move backend tests to their own file | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add support for using InsnOut as memory operand base | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Rename transform_insns to forward_pass | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add assert | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Remove unused code, add backend asm test | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Port bitwise not, gen_check_ints() | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add atomic counter increment instruction | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Port over putnil, putobject, and gen_leave() | Maxime Chevalier-Boisvert | |
| * Remove x86-64 dependency from codegen.rs * Port over putnil and putobject * Port over gen_leave() * Complete port of gen_leave() * Fix bug in x86 instruction splitting | |||
| 2022-08-29 | Port gen_leave_exit(), add support for labels to backend | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add cpush and cpop IR instructions | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add conditional jumps | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Map comments in backend | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Have Assembler::compile() return a list of GC offsets | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Remove x86_64 dependency in core.rs | Maxime Chevalier-Boisvert | |
| 2022-08-29 | * Arm64 Beginnings (https://github.com/Shopify/ruby/pull/291) | Maxime Chevalier-Boisvert | |
| * Initial setup for aarch64 * ADDS and SUBS * ADD and SUB for immediates * Revert moved code * Documentation * Rename Arm64* to A64* * Comments on shift types * Share sig_imm_size and unsig_imm_size | |||
| 2022-08-29 | Add test for lea and ret. Fix codegen for lea and ret. | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Change codegen.rs to use backend Assembler directly | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Implement gc offset logic | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Load GC Value operands into registers | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add CCall IR insn, implement gen_swap() | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add gen_dupn | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add test with register reuse | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Fix issue with load, gen_dup | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Implement target-specific insn splitting with Kevin. Add tests. | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Make assembler methods public, sketch gen_dup with new backend | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Fix bug with asm.comment() | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Bias register allocator to reuse first operand | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Add dbg!() for Assembler. Fix regalloc issue. | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Function to map from Opnd => X86Opnd | Maxime Chevalier-Boisvert | |
| 2022-08-29 | Start work on platform-specific codegen | Maxime Chevalier-Boisvert | |
 |
index : ruby.git | |
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