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authorAaron Patterson <tenderlove@ruby-lang.org>2021-07-15 13:35:19 -0700
committerAlan Wu <XrXr@users.noreply.github.com>2021-10-20 18:19:38 -0400
commit84a1e04e5873e511c8454983c3c34c6494bc5491 (patch)
tree8d23d48750f215bc0a6c74f034fb92764a4bbcce /yjit_core.h
parent2a59bd73125053a8f5a8d6ec129ef81f3da82fad (diff)
Change register definitions to match the entry point calling convention
The JIT entry point passes the CFP as RSI and the EC as RDI. Lets match that so we don't have to shuffle registers around.
Diffstat (limited to 'yjit_core.h')
-rw-r--r--yjit_core.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/yjit_core.h b/yjit_core.h
index cff46648cc..c6790e4f00 100644
--- a/yjit_core.h
+++ b/yjit_core.h
@@ -5,8 +5,8 @@
#include "yjit_asm.h"
// Register YJIT receives the CFP and EC into
-#define REG_CFP RDI
-#define REG_EC RSI
+#define REG_CFP RSI
+#define REG_EC RDI
// Register YJIT loads the SP into
#define REG_SP RDX