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authorAGSaidi <AGSaidi@users.noreply.github.com>2020-08-13 12:15:54 -0500
committerGitHub <noreply@github.com>2020-08-14 02:15:54 +0900
commit511b55bcefc81c036294dc9a544d14bd342acd3b (patch)
tree005ed74167f0a3a16363e09b6f354a63e8a56726 /vm_exec.c
parent787cb0fd868bb6de40dcc78fcc39c28a96c7d561 (diff)
Enable arm64 optimizations that exist for power/x86 (#3393)
* Enable unaligned accesses on arm64 64-bit Arm platforms support unaligned accesses. Running the string benchmarks this change improves performance by an average of 1.04x, min .96x, max 1.21x, median 1.01x * arm64 enable gc optimizations Similar to x86 and powerpc optimizations. | |compare-ruby|built-ruby| |:------|-----------:|---------:| |hash1 | 0.225| 0.237| | | -| 1.05x| |hash2 | 0.110| 0.110| | | 1.00x| -| * vm_exec.c: improve performance for arm64 | |compare-ruby|built-ruby| |:------------------------------|-----------:|---------:| |vm_array | 26.501M| 27.959M| | | -| 1.06x| |vm_attr_ivar | 21.606M| 31.429M| | | -| 1.45x| |vm_attr_ivar_set | 21.178M| 26.113M| | | -| 1.23x| |vm_backtrace | 6.621| 6.668| | | -| 1.01x| |vm_bigarray | 26.205M| 29.958M| | | -| 1.14x| |vm_bighash | 504.155k| 479.306k| | | 1.05x| -| |vm_block | 16.692M| 21.315M| | | -| 1.28x| |block_handler_type_iseq | 5.083| 7.004| | | -| 1.38x|
Notes
Notes: Merged-By: nurse <naruse@airemix.jp>
Diffstat (limited to 'vm_exec.c')
-rw-r--r--vm_exec.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/vm_exec.c b/vm_exec.c
index ce2e053ee7..7aa56f6ad6 100644
--- a/vm_exec.c
+++ b/vm_exec.c
@@ -57,6 +57,9 @@ static void vm_insns_counter_count_insn(int insn) {}
#elif defined(__GNUC__) && defined(__powerpc64__)
#define DECL_SC_REG(type, r, reg) register type reg_##r __asm__("r" reg)
+#elif defined(__GNUC__) && defined(__aarch64__)
+#define DECL_SC_REG(type, r, reg) register type reg_##r __asm__("x" reg)
+
#else
#define DECL_SC_REG(type, r, reg) register type reg_##r
#endif
@@ -93,6 +96,11 @@ vm_exec_core(rb_execution_context_t *ec, VALUE initial)
DECL_SC_REG(rb_control_frame_t *, cfp, "15");
#define USE_MACHINE_REGS 1
+#elif defined(__GNUC__) && defined(__aarch64__)
+ DECL_SC_REG(const VALUE *, pc, "19");
+ DECL_SC_REG(rb_control_frame_t *, cfp, "20");
+#define USE_MACHINE_REGS 1
+
#else
register rb_control_frame_t *reg_cfp;
const VALUE *reg_pc;