diff options
| author | Aaron Patterson <tenderlove@ruby-lang.org> | 2021-07-15 13:35:19 -0700 |
|---|---|---|
| committer | Alan Wu <XrXr@users.noreply.github.com> | 2021-10-20 18:19:38 -0400 |
| commit | 84a1e04e5873e511c8454983c3c34c6494bc5491 (patch) | |
| tree | 8d23d48750f215bc0a6c74f034fb92764a4bbcce | |
| parent | 2a59bd73125053a8f5a8d6ec129ef81f3da82fad (diff) | |
Change register definitions to match the entry point calling convention
The JIT entry point passes the CFP as RSI and the EC as RDI. Lets match
that so we don't have to shuffle registers around.
| -rw-r--r-- | yjit_codegen.c | 7 | ||||
| -rw-r--r-- | yjit_core.h | 4 |
2 files changed, 2 insertions, 9 deletions
diff --git a/yjit_codegen.c b/yjit_codegen.c index 7f12ab7b4f..28721585dd 100644 --- a/yjit_codegen.c +++ b/yjit_codegen.c @@ -365,13 +365,6 @@ yjit_entry_prologue(const rb_iseq_t *iseq) uint8_t *code_ptr = cb_get_ptr(cb, cb->write_pos); ADD_COMMENT(cb, "yjit prolog"); - // Fix registers for YJIT. The MJIT callback puts the ec in RDI - // and the CFP in RSI, but REG_CFP == RDI and REG_EC == RSI - mov(cb, REG0, RDI); // EC - mov(cb, REG1, RSI); // CFP - mov(cb, REG_EC, REG0); - mov(cb, REG_CFP, REG1); - // Load the current SP from the CFP into REG_SP mov(cb, REG_SP, member_opnd(REG_CFP, rb_control_frame_t, sp)); diff --git a/yjit_core.h b/yjit_core.h index cff46648cc..c6790e4f00 100644 --- a/yjit_core.h +++ b/yjit_core.h @@ -5,8 +5,8 @@ #include "yjit_asm.h" // Register YJIT receives the CFP and EC into -#define REG_CFP RDI -#define REG_EC RSI +#define REG_CFP RSI +#define REG_EC RDI // Register YJIT loads the SP into #define REG_SP RDX |