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author | AGSaidi <AGSaidi@users.noreply.github.com> | 2020-08-13 12:15:54 -0500 |
---|---|---|
committer | GitHub <noreply@github.com> | 2020-08-14 02:15:54 +0900 |
commit | 511b55bcefc81c036294dc9a544d14bd342acd3b (patch) | |
tree | 005ed74167f0a3a16363e09b6f354a63e8a56726 | |
parent | 787cb0fd868bb6de40dcc78fcc39c28a96c7d561 (diff) |
Enable arm64 optimizations that exist for power/x86 (#3393)
* Enable unaligned accesses on arm64
64-bit Arm platforms support unaligned accesses.
Running the string benchmarks this change improves performance
by an average of 1.04x, min .96x, max 1.21x, median 1.01x
* arm64 enable gc optimizations
Similar to x86 and powerpc optimizations.
| |compare-ruby|built-ruby|
|:------|-----------:|---------:|
|hash1 | 0.225| 0.237|
| | -| 1.05x|
|hash2 | 0.110| 0.110|
| | 1.00x| -|
* vm_exec.c: improve performance for arm64
| |compare-ruby|built-ruby|
|:------------------------------|-----------:|---------:|
|vm_array | 26.501M| 27.959M|
| | -| 1.06x|
|vm_attr_ivar | 21.606M| 31.429M|
| | -| 1.45x|
|vm_attr_ivar_set | 21.178M| 26.113M|
| | -| 1.23x|
|vm_backtrace | 6.621| 6.668|
| | -| 1.01x|
|vm_bigarray | 26.205M| 29.958M|
| | -| 1.14x|
|vm_bighash | 504.155k| 479.306k|
| | 1.05x| -|
|vm_block | 16.692M| 21.315M|
| | -| 1.28x|
|block_handler_type_iseq | 5.083| 7.004|
| | -| 1.38x|
Notes
Notes:
Merged-By: nurse <naruse@airemix.jp>
-rw-r--r-- | gc.c | 13 | ||||
-rw-r--r-- | gc.h | 2 | ||||
-rw-r--r-- | include/ruby/internal/config.h | 2 | ||||
-rw-r--r-- | regint.h | 2 | ||||
-rw-r--r-- | siphash.c | 2 | ||||
-rw-r--r-- | st.c | 2 | ||||
-rw-r--r-- | vm_exec.c | 8 |
7 files changed, 28 insertions, 3 deletions
@@ -1115,6 +1115,19 @@ tick(void) return val; } +#elif defined(__aarch64__) && defined(__GNUC__) +typedef unsigned long tick_t; +#define PRItick "lu" + +static __inline__ tick_t +tick(void) +{ + unsigned long val; + __asm__ __volatile__ ("mrs %0, cntvct_el0", : "=r" (val)); + return val; +} + + #elif defined(_WIN32) && defined(_MSC_VER) #include <intrin.h> typedef unsigned __int64 tick_t; @@ -8,6 +8,8 @@ #define SET_MACHINE_STACK_END(p) __asm__ __volatile__ ("movl\t%%esp, %0" : "=r" (*(p))) #elif defined(__powerpc64__) && defined(__GNUC__) #define SET_MACHINE_STACK_END(p) __asm__ __volatile__ ("mr\t%0, %%r1" : "=r" (*(p))) +#elif defined(__aarch64__) && defined(__GNUC__) +#define SET_MACHINE_STACK_END(p) __asm__ __volatile__ ("mov\t%0, sp" : "=r" (*(p))) #else NOINLINE(void rb_gc_set_stack_end(VALUE **stack_end_p)); #define SET_MACHINE_STACK_END(p) rb_gc_set_stack_end(p) diff --git a/include/ruby/internal/config.h b/include/ruby/internal/config.h index 49f673ef93..0193275e8b 100644 --- a/include/ruby/internal/config.h +++ b/include/ruby/internal/config.h @@ -103,6 +103,8 @@ # define UNALIGNED_WORD_ACCESS 1 #elif defined(__powerpc64__) # define UNALIGNED_WORD_ACCESS 1 +#elif defined(__aarch64__) +# define UNALIGNED_WORD_ACCESS 1 #elif defined(__mc68020__) # define UNALIGNED_WORD_ACCESS 1 #else @@ -52,7 +52,7 @@ #ifndef UNALIGNED_WORD_ACCESS # if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \ defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || \ - defined(__powerpc64__) || \ + defined(__powerpc64__) || defined(__aarch64__) || \ defined(__mc68020__) # define UNALIGNED_WORD_ACCESS 1 # else @@ -30,7 +30,7 @@ #ifndef UNALIGNED_WORD_ACCESS # if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \ defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || \ - defined(__powerpc64__) || \ + defined(__powerpc64__) || defined(__aarch64__) || \ defined(__mc68020__) # define UNALIGNED_WORD_ACCESS 1 # endif @@ -1662,7 +1662,7 @@ st_values_check(st_table *tab, st_data_t *values, st_index_t size, #ifndef UNALIGNED_WORD_ACCESS # if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \ defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || \ - defined(__powerpc64__) || \ + defined(__powerpc64__) || defined(__aarch64__) || \ defined(__mc68020__) # define UNALIGNED_WORD_ACCESS 1 # endif @@ -57,6 +57,9 @@ static void vm_insns_counter_count_insn(int insn) {} #elif defined(__GNUC__) && defined(__powerpc64__) #define DECL_SC_REG(type, r, reg) register type reg_##r __asm__("r" reg) +#elif defined(__GNUC__) && defined(__aarch64__) +#define DECL_SC_REG(type, r, reg) register type reg_##r __asm__("x" reg) + #else #define DECL_SC_REG(type, r, reg) register type reg_##r #endif @@ -93,6 +96,11 @@ vm_exec_core(rb_execution_context_t *ec, VALUE initial) DECL_SC_REG(rb_control_frame_t *, cfp, "15"); #define USE_MACHINE_REGS 1 +#elif defined(__GNUC__) && defined(__aarch64__) + DECL_SC_REG(const VALUE *, pc, "19"); + DECL_SC_REG(rb_control_frame_t *, cfp, "20"); +#define USE_MACHINE_REGS 1 + #else register rb_control_frame_t *reg_cfp; const VALUE *reg_pc; |