From f6661f50854e0cdccb03ee516a21ce62adf6c802 Mon Sep 17 00:00:00 2001 From: Koichi Sasada Date: Fri, 16 Oct 2020 15:20:40 +0900 Subject: sync RClass::ext::iv_index_tbl iv_index_tbl manages instance variable indexes (ID -> index). This data structure should be synchronized with other ractors so introduce some VM locks. This patch also introduced atomic ivar cache used by set/getinlinecache instructions. To make updating ivar cache (IVC), we changed iv_index_tbl data structure to manage (ID -> entry) and an entry points serial and index. IVC points to this entry so that cache update becomes atomically. --- iseq.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'iseq.c') diff --git a/iseq.c b/iseq.c index 05a77c8ed6..2f10cd6223 100644 --- a/iseq.c +++ b/iseq.c @@ -23,6 +23,7 @@ #include "id_table.h" #include "internal.h" #include "internal/bits.h" +#include "internal/class.h" #include "internal/compile.h" #include "internal/error.h" #include "internal/file.h" @@ -180,6 +181,20 @@ iseq_extract_values(VALUE *code, size_t pos, iseq_value_itr_t * func, void *data } } break; + case TS_IVC: + { + IVC ivc = (IVC)code[pos + op_no + 1]; + if (ivc->entry) { + if (RB_TYPE_P(ivc->entry->class_value, T_NONE)) { + rb_bug("!! %u", ivc->entry->index); + } + VALUE nv = func(data, ivc->entry->class_value); + if (ivc->entry->class_value != nv) { + ivc->entry->class_value = nv; + } + } + } + break; case TS_ISE: { union iseq_inline_storage_entry *const is = (union iseq_inline_storage_entry *)code[pos + op_no + 1]; -- cgit v1.2.3