* Change IncrCounter lowering on AArch64

Previously we were using LDADDAL which is not available on
Graviton 1 chips. Instead, we're going to use an exclusive
load/store group through the LDAXR/STLXR instructions.

* Update yjit/src/backend/arm64/mod.rs

Co-authored-by: Maxime Chevalier-Boisvert <maximechevalierb@gmail.com>

* LDR instruction for AArch64

* Split loads in arm64_split when memory address displacements do not fit

* Move to/from SP on AArch64

* Consolidate loads and stores

* Implement LDR post-index and LDR pre-index for AArch64

* Implement STR post-index and STR pre-index for AArch64

* Module entrypoints for LDR pre/post -index and STR pre/post -index

* Use STR (pre-index) and LDR (post-index) to implement push/pop

* Go back to using MOV for to/from SP

* CSEL on AArch64

* Implement various Op::CSel* instructions

* Port print_int to the new backend

* Tests for print_int and print_str

* ADR and ADRP for AArch64

* Implement Op::Jbe on X86

* Lera instruction

* Op::BakeString

* LeaPC -> LeaLabel

* Port print_str to the new backend

* Port print_value to the new backend

* Port print_ptr to the new backend

* Write null-terminators in Op::BakeString

* Fix up rebase issues on print-str port

* Add back in panic for X86 backend for unsupported instructions being lowered

* Fix target architecture